Compact model of MOSFET electron tunneling current through ultra-thin SiO2 and high-k gate stacks

Device Research Conference - Conference Digest, DRC

Volumn 2003-January, Issue , 2003, Pages 47-48

  Li, Fei ^a   Mudanai, S P ^b   Fan, Yang Yu ^a   Register, L F ^a   Banerjee, S K ^a  

^a The University of Texas at Austin   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Charge carrier processes; Computational modeling; Electrons; High K dielectric materials; High K gate dielectrics; Leakage current; MOSFET circuits; Predictive models; Quantum computing; Tunneling

Indexed keywords

DIELECTRIC MATERIALS; ELECTRON TUNNELING; ELECTRONS; GATE DIELECTRICS; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; QUANTUM COMPUTERS; SILICA;

CHARGE CARRIER PROCESS; COMPUTATIONAL MODEL; HIGH- K GATE DIELECTRICS; MOSFET CIRCUITS; PREDICTIVE MODELS; QUANTUM COMPUTING;

HIGH-K DIELECTRIC;

EID: 84942585293     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2003.1226865     Document Type: Conference Paper

References (3)

1. UTQUANT 3.0, University of Texas at Austin, 2001.
2. S. Mudanai et al., DRC, 2001.
3. L. F. Register, E. Rosenbaum and K. Yang, APL 74, (1999).