Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation

IEEE Transactions on Computers

Volumn 40, Issue 9, 1991, Pages 989-995

  Takagi, Naofumi ^a   Yajima, Shuzo ^a   Asada, Tohru ^b  

^a KYOTO UNIVERSITY   (Japan)

^b NONE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84941863581     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.83660     Document Type: Article

References (12)

1. J. Voider, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput, vol. EC-8, pp. 330–334, Sept. 1959.
2. J. S. Walther, “A unified algorithm for elementary functions,” in Proc. AFIPS Spring Joint Comput. Conf., 1971, pp. 379–385.
3. G. L. Haviland and A. A. Tuszynsky, “A CORDIC arithmetic processor chip,” IEEE Trans. Comput., vol. C-29, pp. 68–79, Feb. 1980.
4. H. M. Ahmed, J. M. Delosme, and M. Morf, “Highly concurrent computing structures for matrix arithmetic and signal processing,” IEEE Comput. Mag., vol. 15, no. 1, pp. 65–82, Jan. 1982.
5. J. R. Cavallaro and F. T. Luk, “CORDIC arithmetic for an SVD processor,” in Proc. 8th Symp. Comput. Arithmetic, May 1987, pp. 113–120.
6. M. D. Ercegovac and T. Lang, “Redundant and on-line CORDIC: Application to matrix triangulation and SVD,” UCLA Comput. Sci. Dep. Rep., CSD-870046 Sep. 1987.
7. —, “Fast cosine/sine implementation using on-line CORDIC,” in Proc. 21st Asilomar Conf. Signals, Syst., Comput., 1987.
8. N. Takagi, T. Asada, and S. Yajima, “A hardware algorithm for computing sine and cosine using redundant binary representation,” Trans. IECE Japan, vol. J69-D, no. 6, pp. 841–847, June 1986 (in Japanese). English translated version is available in Systems and Computers in Japan, vol. 18, no. 8, pp. 1–9, Aug. 1987.
9. T. Asada, N. Takagi, and S. Yajima, “Acceleration of a hardware algorithm for calculating sine and cosine using redundant binary representation,” in IEICE Japan, Nat. Convention Rec., part 2, Mar. 1987, pp. 408–409 (in Japanese).
10. A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comput., vol. EC-10, pp. 389–400, Sept. 1961.
11. C. Y. Chow and J.E. Robertson, “Logical design of a redundant binary adder,” in Proc. 4th Symp. Comput. Arithmetic, Oct. 1978, pp. 109–115.
12. T. Asada, N. Takagi, and S. Yajima, “Algorithms based on CORDIC for calculating hyperbolic functions using redundant binary representation,” in Proc. 34th Nat. Convention IPS Japan, Mar. 1987, pp. 33–34 (in Japanese).