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Volumn 31, Issue 12, 1984, Pages 1693-1700

Optimum Design of Power MOSFET's

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EID: 84941490928     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21773     Document Type: Article
Times cited : (84)

References (17)
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    • Feb.
    • S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, p. 356, Feb. 1980.
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    • V. A. K. Temple, “Ideal FET doping profile,” IEEE Trans. Electron Devices, vol. ED-30, no. 6, p. 619, June 1983.
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  • 7
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    • Jan.
    • K. Board, D. Byrne, and M. S. Towers “The optimization of on-resistance resistance in vertical DMOS power devices with linear and hexagonal surface geometries,” IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 75–80, Jan. 1984.
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  • 8
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    • Sept.
    • P. L. Hower and M. J. Geisler “Comparison of various source-gate gate geometries of power MOSFET's,” IEEE Trans. Electron Devices, vol. ED-28, no. 9, pp. 1098–4101, Sept. 1981.
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    • Hower, P.L.1    Geisler, M.J.2
  • 11
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  • 15
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    • C. Hu and M-H. Chi “Second breakdown of vertical power MOSFET's,” IEEE Trans. Electron Devices, vol. ED-29, no. 8, pp. 1287-1239, Aug. 1982.
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    • Hu, C.1    Chi, M.-H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.