Effects of Substrate Resistance on CMOS Latchup Holding Voltages

IEEE Transactions on Electron Devices

Volumn 34, Issue 11, 1987, Pages 2309-2316

  Hu, Chenming ^c  

^a INTEL CORPORATION   (United States)

^b NEC CORPORATION   (Japan)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84941460275     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1987.23237     Document Type: Article

References (14)

1. G. Hu, “A better understanding of CMOS latchup,” IEEE Trans. Electron Devices, vol. ED-31, p. 62, Jan. 1984.
2. G. Hu and R. H. Bruce, “A CMOS structure with high latchup holding voltage,” IEEE Electron Device Lett., vol. EDL-5, p. 211, May 1984.
3. R. D. Rung, H. Momose, and Y. Nagakubo, “Deep trench isolated CMOS devices,” in IEDM Tech. Dig., 1982.
4. R. K. Gupta, I. Sakai, C. Hu, “Analysis of latch-up holding voltage for shallow trench CMOS,” Electron. Lett., vol. 22, no. 23, Nov. 1986.
5. R. R. Troutman and M. J. Hargrove, “Transmission line model for latchup in CMOS circuits,” in Symp. VLSI Technol. Tech. Dig., p. 56, 1983.
6. R. D. Rung, “Trench isolation prospects for application in CMOS VLSI,” in IEDM Tech. Dig., pp. 574–577, 1984.
7. K. W. Terrill and C. Hu, “Substrate resistance calculation for latchup up modeling,” IEEE Trans. Electron Devices, vol. ED-31, no. 9, p. 1152, 1984.
8. H. P. Zappe, R. K. Gupta, K. W. Terrill, and C. Hu, “Floating well CMOS and latchup,” IEDM Tech. Dig., p. 517, Dec. 1985.
9. J. Y. Chen, “CMOS—The emerging VLSI technology,” IEEE Circuits Devices Mag., vol. 2, p. 21, Mar. 1986.
10. Y. Taur, W. H. Chang, and R. H. Dennard, “Characterization and modeling of a latchup-free 1-micron CMOS technology,” in IEDM Tech. Dig., p. 398, 1984.
11. F. S. Lai et al., in IEDM Tech. Dig., pp. 513–516, 1985.
12. Y. Niitsu, Toshiba Corp., Japan, personal communication.
13. A. G. Lewis “Latchup suppression in fine-dimension shallow p-well CMOS circuits,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1472–1481, Oct. 1984.
14. K. W. Terrill, P. F. Byrne, H. P. Zappe, N. W. Cheung, and C. Hu, “A new method for preventing CMOS latchup,” in IEDM Tech. Dig., p. 406, Dec. 1984.