Design and Experimental Technology for 0.1-μm Gate-Length Low-Temperature Operation FET's

IEEE Electron Device Letters

Volumn 8, Issue 10, 1987, Pages 463-466

  Sai Halasz, George A ^a   Wordeman, Matthew R ^a   Kern, D P ^a   Ganin, E ^a   Rishton, S ^a   Zicherman, D S ^a   Schmid, H ^a   Polcari, Michael R ^a   Ng, H Y ^a   Restle, P J ^a   Chang, T H P ^a   Dennard, Robert H ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84941448723     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26695     Document Type: Article

References (11)

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9. S. Y. Chou, D. A. Antoniadis, and H. I. Smith, “Observation of electron velocity overshoot in sub-100 nm-channel MOSFET's in silicon,” IEEE Electron Device Lett., vol. EDL-6, p. 665, 1985.
10. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, “Electron velocity overshoot at 300 K and 77 K in silicon MOSFET's with submicron channel lengths.” in IEDM Tech. Dig., 1986, p. 824.
11. T. Kobayashi and K. Saito. “Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 788, 1985.