IDDQ data analysis using current signature

Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

Volumn 1998-November, Issue , 1998, Pages 37-42

  Li, J C M ^a   McCluskey, E J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TESTING;

BOOLEAN TESTS; CURRENT SIGNATURE ANALYSIS; CURRENT SIGNATURES; DEFECT CLASS; DIFFERENT CLASS; IDDQ TESTING; NON-FUNCTIONAL; TOTAL VARIANCE;

DEFECTS;

EID: 84941349758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1998.730730     Document Type: Conference Paper

References (15)

1. P. Maxwell, et al., "The Effectiveness of IDDQ, Functional and Scan Tests: How many fault coverage do we need?" Proc. International Test Conference, pp. 168-177, Dec. 1992.
2. Rodriguez-Montanes, et al., "Current vs. logic Testing of Gate Oxide short, Floating Gate and Bridging Failures in CMOS, " Proc. International Test Conference, pp. 510-518, Oct. 1991.
3. J.M. Soden and C.F. Hawkins, "IDDQ Testing: Issues Present and Future", IEEE Design and Test of Computers, pp. 61-65, Winter 1996.
4. A.E. Gattiker and W. Maly, "Current Signatures, " Proc. IEEE VLSI Test Symposium, pp. 112-117, April 1996.
5. A.E. Gattiker and W. Maly, "Current Signatures: Application, " Proc. International Test Conference, pp. 156-165, Nov. 1997.
6. P. Franco, et al., "An Experimental Chip to Evaluate Test techniques Chip and Experiment Design, " Proc. International Test Conference, pp. 653-662, Oct. 1995.
7. P. Nigh, et al., "So What Is An Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment, " Proc. International Test Conference, pp. 1037-1038, Nov. 1997.
8. P. Nigh, et al., "An Experiment Study Comparing the Relative Effectiveness of Functional, Scan, IDDQ and Delay-fault Testing, " IEEE VLSI Test Symposium, pp. 459-464, April 1997.
9. P. Nigh, et al., "Failure Analysis of Timing and IDDQonly Failure from the SEMATECH Test Methods Experiment, " Proc. International Test Conference, 1998.
10. C. Henderson and J. Soden, ÒSignature Analysis for IC Diagnosis and Failure Analysis, " Proc. International Test Conference, pp. 310-318, Nov. 1997.
11. J.T.-Y. Chang et al., "Experimental Result for IDDQ and VLV Testing, " Proc. IEEE VLSI Test Symposium, pp. 118-123, April 1998.
12. P. Franco, et al., "Analysis and Detection of Timing Failures in an Experimental Test Chip, " P r o c. International Test Conference, pp. 691- 700, Oct. 1996.
13. J.T.-Y. Chang et al., "Quantitative Analysis of Very Low-Voltage Testing, " Proc. IEEE VLSI Test Symposium, pp. 332-337, April 1996.
14. S. Davidson, "Is IDDQ yield Loss Inevitable?, " Proc. International Test Conference, pp. 572-578, 1994.
15. T.R.Henry and T.Soo, "Burn-in Elimination of a High Volume Microprocessor Using IDDQ, " P r o c. International Test Conference, pp. 242-249, Oct. 1996.