Parametric Study on Pressureless Sintering of Nanosilver Paste to Bond Large-Area (≥100 mm2) Power Chips at Low Temperatures for Electronic Packaging

Journal of Electronic Materials

Volumn 44, Issue 10, 2015, Pages 3973-3984

  Fu, Shancan ^a   Mei, Yunhui ^a   Li, Xin ^a   Ning, Puqi ^c   Lu, Guo Quan ^a,b  

^a TIANJIN UNIVERSITY   (China)

^b VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^c INSTITUTE OF ELECTRICAL ENGINEERING   (China)

Author keywords

die attachment; low temperature sintering; microstructures; shear strength; Silver nanoparticles

Indexed keywords

CHIP SCALE PACKAGES; ELECTRONICS PACKAGING; HEATING RATE; MICROSTRUCTURE; NANOPARTICLES; PORE SIZE; SHEAR STRENGTH; SILVER; TAGUCHI METHODS;

DIE ATTACHMENT; ELECTRONIC PACKAGING; LOW-TEMPERATURE SINTERING; MICROSTRUCTURE AND MECHANICAL PROPERTIES; PRESSURE-LESS SINTERING; PRESSURELESS-SINTERED; SILVER NANOPARTICLES; SINTERING TEMPERATURES;

SINTERING;

EID: 84940795865     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-015-3842-1     Document Type: Article

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