A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 468-469

  Brandolini, Massimo ^a   Shin, Young ^a   Raviprakash, Karthik ^a   Wang, Tao ^a   Wu, Rong ^a   Geddada, Hemasundar M ^a   Ko, Yen Jen ^b   Ding, Yen ^b   Huang, Chun Sheng ^b   Shin, Wei Ta ^b   Hsieh, Ming Hung ^b   Chou, Wei Te ^b   Li, Tianwei ^a   Shrivastava, Ayaskant ^a   Chen, Yi Chun ^a   Hung, Juo Jung ^a   Cusmai, Giuseppe ^a   Wu, Jiangfeng ^a   Zhang, Mo M ^a   Unruh, Greg ^a   Venes, Ardie ^a   Huang, Hung Sen ^a   Chen, Chun Ying ^a   more..

^a BROADCOM CORPORATION   (United States)

^b Broadcom Ltd   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; PIPELINES;

BROADBAND SATELLITES; CALIBRATION TECHNIQUES; FUNCTIONAL BLOCK DIAGRAMS; HYBRID ARCHITECTURES; POWER EFFICIENCY; RESOLUTION REQUIREMENTS; TIME-INTERLEAVED; TIME-INTERLEAVING;

ANALOG TO DIGITAL CONVERSION;

EID: 84940765817     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063129     Document Type: Conference Paper

References (6)

1. E. Janssen, et al., "An 11b 3.6GS/s TI SAR ADC in 65nm CMOS, " ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2013.
2. N.L. Dortz, et al., "A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS, " ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2014.
3. D. Stepanovic and B. Nikolic, "A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS, " Symp. VLSI Circuits, pp. 84-85, 2012.
4. J. Wu, et al., "A 5.4GS/s 12b 500mW Pipeline ADC in 28nm CMOS", Symp. VLSI Circuits, pp. 92-93, 2013.
5. P. Huang, et al., "SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration", IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1893-1903, 2011.
6. B. Shen, et al., "An 8.5 mW, 0.07 mm2 ADPLL in 28nm CMOS with Sub-ps Resolution TDC and