A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 406-407

  Yu, Kunzhi ^a   Li, Hao ^b   Li, Cheng ^c   Titriku, Alex ^a   Shafik, Ayman ^a   Wang, Binhao ^d   Wang, Zhongkai ^b   Bai, Rui ^c   Chen, Chin Hui ^c   Fiorentino, Marco ^b,d   Chiang, Patrick Yin ^a   Palermo, Samuel ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b OREGON STATE UNIVERSITY   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CONTINUOUS TIME SYSTEMS; DROPS; ENERGY EFFICIENCY; MODULATION; OSCILLISTORS; STABILIZATION;

ADAPTIVE EQUALIZATION; CONTINUOUS TIME LINEAR EQUALIZER (CTLE); FABRICATION TOLERANCES; HIGH-SPEED MODULATION; INJECTION LOCKED OSCILLATORS; OPTICAL INTERCONNECT; RESONANCE WAVELENGTHS; WAVELENGTH STABILIZATION;

EQUALIZERS;

EID: 84940762076     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063098     Document Type: Conference Paper

References (4)

1. J. Buckwalter, et al., "A Monolithic 25-Gb/s Transceiver with Photonic Ring Modulators and Ge Detectors in a 130nm CMOS SOI Process, " IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1309-1322, June 2012.
2. F. Liu, et al., "10 Gbps, 530fJ/b optical transceiver circuits in 40nm CMOS, " IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2049-2067, Sept. 2012.
3. C. Li, et al., "Silicon Photonic Transceiver Circuits with Microring Resonator Bias-Based Wavelength Stabilization in 65-nm CMOS, " IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1419-1436, June 2014.
4. D. Li, et al., "A Low-Noise Design Technique for High-Speed CMOS Optical Receivers, " IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1437-1447, June 2014.