A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

2015 IEEE 7th International Memory Workshop, IMW 2015

Volumn , Issue , 2015, Pages

  Do, Nhan ^a   Tee, Latt ^a   Hariharan, Santosh ^a   Lemke, Steven ^a   Tadayoni, Mandana ^a   Yang, Will ^a   Wu, Mt ^a   Kim, Jinho ^a   Chen, Yueh Hsin ^a   Su, Chien Sheng ^a   Tiwari, Vipin ^a   Zhou, Stephen ^a   Qian, Rodger ^a   Yue, Ian ^a  

^a MICROCHIP TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; RELIABILITY;

HIGH-DENSITY ARRAYS; LOGIC PROCESS; LOW POWER; MULTIPLE LOGIC; PERFORMANCE AND RELIABILITIES; SPLIT GATES; SPLIT-GATE FLASH MEMORY; TEMPERATURE RANGE;

COMPUTER CIRCUITS;

EID: 84939517972     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2015.7150267     Document Type: Conference Paper

References (2)

1. Y. Tkachev, X. Liu, and A. Kotov, "Floating gate corner-enhanced polypoly tunneling in split-gate Flash memory cells," IEEE Trans. Electron Devices, 2012, Vol. 29, pp. 5-11
2. Y. K. Lee et al, "A 45 nm Logic Compatible 4Mb Split-Gate Embedded Flash with 1M Cycling Endurance", IMW 2014, pp.75-78.