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Volumn , Issue , 1986, Pages 481-489

Hierarchical global wiring for custom chip design

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS;

EID: 84939377458     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586132     Document Type: Conference Paper
Times cited : (6)

References (13)
  • 2
    • 0020828718 scopus 로고
    • Hierarchical wire routing
    • October
    • M. Burstein and R. Pelavin, Hierarchical wire routing, IEEE Trans, on CAD, Vol. CAD-2, No. 4, pp. 223-234, October 1983.
    • (1983) IEEE Trans, on CAD , vol.CAD-2 , Issue.4 , pp. 223-234
    • Burstein, M.1    Pelavin, R.2
  • 4
    • 34250246836 scopus 로고
    • A fast algorithm for steiner trees
    • L. Kou, G. Markowsky and L. Berman, A fast algorithm for steiner trees, Acta Informatica, Vol. 15, pp. 141-145, 1981.
    • (1981) Acta Informatica , vol.15 , pp. 141-145
    • Kou, L.1    Markowsky, G.2    Berman, L.3
  • 11
    • 0020833410 scopus 로고
    • Routing techniques for gate arrays
    • October
    • B. S. Ting and B. N. Tien, Routing techniques for gate arrays, IEEE Trans, on Computer-Aided Design, Vol. CAD-2, No. 4, pp. 301-312, October 1983.
    • (1983) IEEE Trans, on Computer-Aided Design , vol.CAD-2 , Issue.4 , pp. 301-312
    • Ting, B.S.1    Tien, B.N.2
  • 12
  • 13
    • 0020767156 scopus 로고
    • Steiner trees, partial 2-trees, and minimum ifi networks
    • J. A. Wald and C. J. Colbourn, Steiner trees, partial 2-trees, and minimum IFI networks, Networks, Vol. 13, pp. 159-167, 1983.
    • (1983) Networks , vol.13 , pp. 159-167
    • Wald, J.A.1    Colbourn, C.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.