메뉴 건너뛰기




Volumn 32, Issue 2, 1985, Pages 333-343

Performance Limits of CMOS ULSI

Author keywords

[No Author keywords available]

Indexed keywords


EID: 84939365158     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.21947     Document Type: Article
Times cited : (28)

References (35)
  • 1
    • 0020879241 scopus 로고
    • Theoretical, practical, and analogical limits in VLSI
    • Dec.
    • J. Meindl, “Theoretical, practical, and analogical limits in VLSI,” in IEDM Tech. Dig., pp. 8–13, Dec. 1983.
    • (1983) IEDM Tech. Dig. , pp. 8-13
    • Meindl, J.1
  • 2
    • 0018455968 scopus 로고
    • Device down scaling and expected circuit performance
    • Apr.
    • P. Hart et a/., “Device down scaling and expected circuit performance,” IEEE Trans. Electron Devices, pp. 421–429, Apr. 1979.
    • (1979) IEEE Trans. Electron Devices , pp. 421-429
    • Hart, P.1
  • 3
    • 0020125545 scopus 로고
    • A comparison of semiconductor devices for high-speed logic
    • P. Solomon, “A comparison of semiconductor devices for high-speed logic,” Proc. IEEE, pp. 489–509, 1982.
    • (1982) Proc. IEEE , pp. 489-509
    • Solomon, P.1
  • 4
    • 0019666819 scopus 로고
    • CMOS technologies for VLSI circuits
    • S. Kohyama and T. Sato, “CMOS technologies for VLSI circuits,” in Dig. 1981 VLSI Symp., pp. 24–25, 1981.
    • (1981) Dig. 1981 VLSI Symp. , pp. 24-25
    • Kohyama, S.1    Sato, T.2
  • 5
    • 0016506999 scopus 로고
    • Physical limits in digital electronics
    • R. Keyes, “Physical limits in digital electronics,” Proc. IEEE, pp. 740–767,1975.
    • (1975) Proc. IEEE , pp. 740-767
    • Keyes, R.1
  • 6
    • 0000901940 scopus 로고
    • Fundamental limitations in microelectronics—I MOS technology
    • B. Hoeneisen and C. Mead, “Fundamental limitations in microelectronics—I MOS technology,” Solid-State Electron., pp. 819–829, 1972.
    • (1972) Solid-State Electron. , pp. 819-829
    • Hoeneisen, B.1    Mead, C.2
  • 7
    • 0020832969 scopus 로고
    • A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI
    • H. Shichijo, “A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI,” Solid-State Electron., pp. 969–986, 1983.
    • (1983) Solid-State Electron. , pp. 969-986
    • Shichijo, H.1
  • 8
    • 0019248304 scopus 로고
    • Resolution, overlay, and field-size for lithography systems
    • Dec.
    • A. Broers, “Resolution, overlay, and field-size for lithography systems,” in IEDM Tech. Dig., pp. 2–6, Dec. 1980.
    • (1980) IEDM Tech. Dig. , pp. 2-6
    • Broers, A.1
  • 9
    • 0020310803 scopus 로고
    • Titanium disilicide self-aligned source/drain + gate technology
    • Dec.
    • C. Lau et al. “Titanium disilicide self-aligned source/drain + gate technology,” in IEDM Tech. Dig., pp. 714–717, Dec. 1982.
    • (1982) IEDM Tech. Dig. , pp. 714-717
    • Lau, C.1
  • 10
    • 33751514541 scopus 로고
    • Implications of high performance heat sinking for electron devices
    • Oct.
    • D. Tuckerman and R. Pease, “Implications of high performance heat sinking for electron devices” (DRC 81 Abstract), IEEE Trans. Electron Devices, pp. 1230–1231, Oct. 1981.
    • (1981) (DRC 81 Abstract), IEEE Trans. Electron Devices , pp. 1230-1231
    • Tuckerman, D.1    Pease, R.2
  • 11
    • 0018455052 scopus 로고
    • VLSI limitations from drain-induced barrier lowering
    • Apr.
    • R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE Trans. Electron Devices, pp. 461–468, Apr. 1979.
    • (1979) IEEE Trans. Electron Devices , pp. 461-468
    • Troutman, R.1
  • 12
    • 85038061827 scopus 로고
    • Circuit scaling limits for ultra large scale integration
    • Feb.
    • J. Meindl et al., “Circuit scaling limits for ultra large scale integration,” in Dig. Int. Solid State Circuits Conf., pp. 36–37, Feb.1981.
    • (1981) Dig. Int. Solid State Circuits Conf. , pp. 36-37
    • Meindl, J.1
  • 13
    • 84939770291 scopus 로고
    • Performance limits of NMOS and CMOS
    • Feb.
    • J. Pfiester et al., “Performance limits of NMOS and CMOS,” in Dig. Int. Solid State Circuits Conf., pp. 158–159, Feb. 1984.
    • (1984) Dig. Int. Solid State Circuits Conf. , pp. 158-159
    • Pfiester, J.1
  • 14
    • 0020194040 scopus 로고
    • Short-channel MOST threshold voltage model
    • Oct.
    • R. Ratnakumar et al., “Short-channel MOST threshold voltage model,” IEEE J. Solid-State Circuits, pp. 937–948, Oct. 1982.
    • (1982) IEEE J. Solid-State Circuits , pp. 937-948
    • Ratnakumar, R.1
  • 17
    • 0019045194 scopus 로고
    • Nonplanar VLSI device analysis using the solution of Poisson’s equation
    • Aug.
    • J. Greenfield and R. Dutton, “Nonplanar VLSI device analysis using the solution of Poisson’s equation,” IEEE Trans. Electron Devices, pp. 1520–1532, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , pp. 1520-1532
    • Greenfield, J.1    Dutton, R.2
  • 18
    • 0018480027 scopus 로고
    • Characteristics and limitations of scaled-down MOSFET’s due to two-dimensional field effect
    • June
    • H. Masuda et al., “Characteristics and limitations of scaled-down MOSFET’s due to two-dimensional field effect,” IEEE Trans. Electron Devices, pp. 980–996, June 1979.
    • (1979) IEEE Trans. Electron Devices , pp. 980-996
    • Masuda, H.1
  • 19
    • 0018517266 scopus 로고
    • Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET
    • Sept.
    • J. Brews, “ Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET,” IEEE Trans. Electron Devices, pp. 1282–1291, Sept. 1979.
    • (1979) IEEE Trans. Electron Devices , pp. 1282-1291
    • Brews, J.1
  • 22
    • 0019669464 scopus 로고
    • Supply voltage and logic levels for VLSI
    • D. Hodges, “Supply voltage and logic levels for VLSI,” in Dig. 1981 VLSI Symp., pp. 42–43, 1981.
    • (1981) Dig. 1981 VLSI Symp. , pp. 42-43
    • Hodges, D.1
  • 23
    • 0019047095 scopus 로고
    • A limitation of channel length in dynamic memories
    • Aug.
    • J. Nishizawa et al., “A limitation of channel length in dynamic memories,” IEEE Trans. Electron Devices, pp. 1640–1649, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , pp. 1640-1649
    • Nishizawa, J.1
  • 25
    • 0017943688 scopus 로고
    • Design and performance of micron-size devices
    • F. Klaassen, “Design and performance of micron-size devices,” Solid-State Electron., pp. 565–571, 1978.
    • (1978) Solid-State Electron. , pp. 565-571
    • Klaassen, F.1
  • 26
    • 0020294333 scopus 로고
    • Reliability of thin SiO2 films showing intrinsic dielectric integrity
    • Dec.
    • Y. Hokari et al., “Reliability of thin SiO2 films showing intrinsic dielectric integrity,” in IEDM Tech. Dig., pp. 46–49, Dec. 1982.
    • (1982) IEDM Tech. Dig. , pp. 46-49
    • Hokari, Y.1
  • 27
    • 0020952854 scopus 로고
    • The influence of thermal silicon nitride formation on VLSI fabrication
    •   A. Shintani et al., “The influence of thermal silicon nitride formation on VLSI fabrication,” in Dig. 1983 VLSI Symp., pp. 90–91, 1983.
    • (1983) Dig. 1983 VLSI Symp. , pp. 90-91
    • Shintani, A.1
  • 28
    • 0020247421 scopus 로고
    • Nitrided-oxides for thin gate dielectrics in MOS devices
    • Dec.
    • H. Grinolds et al., “Nitrided-oxides for thin gate dielectrics in MOS devices,” in IEDM Tech. Dig., pp. 42–45, Dec. 1982.
    • (1982) IEDM Tech. Dig. , pp. 42-45
    • Grinolds, H.1
  • 29
    • 0021406605 scopus 로고
    • Generalized scaling theory and its application to a 1/4 micron MOSFET design
    • Apr.
    • G. Baccarani et al., “Generalized scaling theory and its application to a 1/4 micron MOSFET design,” IEEE Trans. Electron Devices, pp. 452–462, Apr. 1984.
    • (1984) IEEE Trans. Electron Devices , pp. 452-462
    • Baccarani, G.1
  • 30
    • 0039956433 scopus 로고
    • Generalized guide for MOSFET miniaturization
    • Jan.
    • J. Brews et al., “Generalized guide for MOSFET miniaturization,” IEEE Electron Device Lett., pp. 2–4, Jan. 1980.
    • (1980) IEEE Electron Device Lett. , pp. 2-4
    • Brews, J.1
  • 32
    • 0020882150 scopus 로고
    • E/D CMOS—A high speed VLSI technology
    • J. Pfiester et al., “E/D CMOS—A high speed VLSI technology,” in Dig. 1983 VLSI Symp., pp. 44–45, 1983.
    • (1983) Dig. 1983 VLSI Symp. , pp. 44-45
    • Pfiester, J.1
  • 33
    • 0001222601 scopus 로고
    • Switching response of complementary-symmetry MOS transistor logic circuits
    • Dec.
    • J. Burns, “Switching response of complementary-symmetry MOS transistor logic circuits,” RCA Rev., pp. 627–659, Dec. 1964.
    • (1964) RCA Rev. , pp. 627-659
    • Burns, J.1
  • 35
    • 0020242301 scopus 로고
    • A half micron MOSFET using double implanted LDD
    • Dec.
    • S. Ogura et al., “A half micron MOSFET using double implanted LDD,” in IEDM Tech. Dig., pp. 718–721, Dec. 1982.
    • (1982) IEDM Tech. Dig. , pp. 718-721
    • Ogura, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.