A 256K CMOS SRAM with Variable Impedance Data-Line Loads

IEEE Journal of Solid-State Circuits

Volumn 20, Issue 5, 1985, Pages 924-928

  Yamamoto, Sho ^a   Tanimura, Nobuyoshi ^a   Nagasawa, Kouichi ^a   Meguro, Satoshi ^a   Yasui, Tokumasa ^a   Minato, Osamu ^a   Masuhara, Toshiaki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84939050891     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1985.1052416     Document Type: Article

References (5)

1. T. Sakurai et al., “A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line,” IEEE J. Solid-State Circuits, pp. 578–585, Oct. 1984.
2. K. C. Hardee et al., ‘’A fault-tolerant 30ns/375 mW 16K×1 NMOS static RAM,” IEEE J. Solid-State Circuits, pp. 435–443, Oct. 1981.
3. S. Konishi et al., “A 64Kb CMOS RAM,” in ISSCC Dig. Tech. Pap., Feb. 1982, pp. 258–259.
4. O. Minato et al., “A 20 ns 64K CMOS SRAM,” in ISSCC Dig. Tech. Pap., Feb. 1984, pp. 222–223.
5. T. Masuhara et al., “A high-speed, low-power Hi-CMOS 4K static RAM,” in ISSCC Dig. Tech. Pap., Feb. 1978, pp. 110–111.