Sub-1/4 μm dual gate CMOS technology using in situ doped polysilicons for N and PMPS gates

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1993, Pages 95-96

  Okazaki, Y ^a   Inokawa, H ^a   Kobayashi, T ^a   Miyake, M ^a   Morimoto, T ^a   Matsuda, T ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); LITHOGRAPHY; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR DOPING; VLSI CIRCUITS;

BORON PENETRATION; CMOS PROCESSS; CMOS TECHNOLOGY; DOPED POLYSILICON; DUAL-GATE CMOS; GATE STRUCTURE; LOW VOLTAGE OPERATION; ULTRA THIN GATE OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 84938452389     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1993.760262     Document Type: Conference Paper

References (1)

1. S. Nakayama, 1991 ECS Spring Meeting, Proc. Int. Symp. on ULSI Science and Technology, p. 9, 1991.