Level based batch scheduling strategy with idle slot reduction under DAG constraints for computational grid

Journal of Systems and Software

Volumn 108, Issue , 2015, Pages 110-133

  Shahid, Mohammad ^a   Raza, Zahid ^a   Sajid, Mohammad ^a  

^a JAWAHARLAL NEHRU UNIVERSITY   (India)

Author keywords

Computational grid; DAG constraints; Level based batch scheduler

Indexed keywords

GRID COMPUTING; MIDDLEWARE; OPTIMIZATION; SCHEDULING;

BATCH SCHEDULERS; COMPUTATIONAL GRIDS; DAG CONSTRAINTS; DIRECT ACYCLIC GRAPHS; GRID ENVIRONMENTS; INTER-MODULE COMMUNICATION; INTERACTIVE APPLICATIONS; OBJECTIVE PARAMETERS;

JOB SHOP SCHEDULING;

EID: 84937775817     PISSN: 01641212     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jss.2015.06.016     Document Type: Article

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