Micro-architecture independent analytical processor performance and power modeling

ISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2015, Pages 32-41

  Van Den Steen, Sam ^a   De Pestel, Sander ^a   Mechri, Moncef ^b   Eyerman, Stijn ^a   Carlson, Trevor ^b   Black Schaffer, David ^b   Hagersten, Erik ^b   Eeckhout, Lieven ^b  

^a GHENT UNIVERSITY   (Belgium)

^b UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODELS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN;

APPLICATION SPECIFIC PROCESSORS; CYCLE-LEVEL SIMULATION; DESIGN SPACE EXPLORATION; MEMORY LEVEL PARALLELISMS; MICRO ARCHITECTURES; PERFORMANCE CONSTRAINTS; PERFORMANCE ESTIMATION; PROCESSOR PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 84937468659     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2015.7095782     Document Type: Conference Paper

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