Bitvalue inference: Detecting and exploiting narrow bitwidth computations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1900, Issue , 2000, Pages 969-979

  Budiu, Mihai ^a   Sakr, Majd ^b   Walker, Kip ^a   Goldstein, Seth C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b UNIVERSITY OF PITTSBURGH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); DATA FLOW ANALYSIS; RECONFIGURABLE HARDWARE;

C PROGRAMS; CODE DETECTION; COMPILER ALGORITHMS; COMPILER OPTIMIZATIONS; FORWARD-AND-BACKWARD; MEDIABENCH; SPECIAL PROCESSOR; SUBSTANTIAL REDUCTION;

PROGRAM COMPILERS;

EID: 84937424951     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44520-x_137     Document Type: Conference Paper

References (14)

1. J. Babb, M. Rinard, A. Moritz, W. Lee, M. Frank, R. Barua, and S. Amarasinghe. Parallelizing applications into silicon. In IEEE/FCCM Symposium on Field- Programmable Custom Computing Machines, Napa Valley, CA, April 1999. MIT.
2. K. Bondalapati and V.K. Prasanna. Dynamic precision management for loop computations on reconfigurable architectures. In IEEE/FCCM Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 1999. Organization: University of Southern California.
3. D. Brooks and M. Martonosi. Dynamically exploiting narrow width operands to improve processor power and performance. In HPCA-5, January 1999. Princeton University.
4. M. Budiu and S.C. Goldstein. Fast compilation for pipelined reconfigurable fabrics. In ACM/FPGA Symposium on Field Programmable Gate Arrays, Monterey, CA, 1999.
5. M. Budiu and S.C. Goldstein. BitValue — Detecting and Exploiting Narrow Bitwidth Computations. Technical Report CMU-CS-00-141, Carnegie Mellon University, June 2000.
6. M. Damiani and G. de Micheli. Don’t care specifications in combinational and synchronous logic circuits. In IEEE Transactions on CAD/ICAS, pages 365–388, 1992.
7. S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, and R. Laufer. Piperench: A coprocessor for streaming multimedia acceleration. In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 28–39, May 1999.
8. C. Lee, M. Potkonjak, and W.H. Mangione-Smith. Mediabench: a tool for evaluating and synthesizing multimedia and communications systems. In Micro-30, 30th annual ACM/IEEE international symposium on Microarchitecture, pages 330–335, 1997.
9. P. Marwedel and G. Goossens, editors. Code generation for embedded processors. Kluwer Academic Press, 1995.
10. A. Peleg, S. Wilkie, and U. Weiser. Intel MMX for multimedia PCs. Communications of the ACM, 40(1):24–38, 1997.
11. Rahul Razdan. PRISC: Programmable reduced instruction set computers. PhD thesis, Harvard University, May 1994. 12. http://www.specbench.org/osg/cpu95/.
12. M. Stephenson, J. Babb, and S. Amarasinghe. Bitwidth analysis with application to silicon compilation. In Proceedings of the SIGPLAN conference on Programming Language Design and Implementation, June 2000.
13. E. Stoltz, M. P. Gerlek, and M. Wolfe. Extended SSA with Factored Use-Def chains to support optimization and parallelism. In Proceedings Hawaii International Conference on Systems Sciences, Maui, Hawaii, Jan. 1994.
14. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S.-W. Liao, C.-W. Tseng, M. Hall, M. Lam, and J. Hennessy. SUIF: An inf rastructure for research on parallelizing and optimizing compilers. In ACM SIGPLAN Notices, volume 29, pages 31–37, December 1994.