Digiltal Logic Simulation in a Time-Based, Table-Driven Environment: Part 2. Parallel Fault Simulation

Computer

Volumn 8, Issue 3, 1975, Pages 38-49

  Thompson, E W ^a   Szygenda, S A ^a  

^a UNIVERSITY OF TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84937349719     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/C-M.1975.218900     Document Type: Article

References (6)

1. E. W. Thompson, S. A. Szygenda, N. Billawala, and R. Pierce, “Timing Analysis for Digital Fault Simulation Using Assignable Delays,” Proceedings of the 11th Design Automation Workshop, 1974.
2. S. A. Szygenda, D. Rouse, and E. Thompson, “A Model and Implementation of a Universal Time Delay Simulator for Large Digital Nets,” Proceedings, SJCC, AFIPS, May 1970.
3. S. A. Szygenda, “TEGAS2-Anatomy of a General-Purpose Test Generation and Simulation System for Digital Logic,” Pro ceedings of the 9th ACM IEEE Design Automation Workshop, June 1972.
4. S. A. Szygenda and E. W. Thompson, “Fault Insertion Techniques and Models for Digital Logic Simulation,” Proceedings, FJBC, AFIPS, December 1972.
5. E. B. Eichelberger, “Hazard Detection in Combinational and Sequential Switching Circuits,” IBM Journal of Research & Development, Vol. 4, pp. 90–99, March 1965.
6. E. W. Thompson and S. A. Szygenda are co-authors of the first feature article. Their biographies appear on page 36.