Energy-efficient parallel software for mobile hand-held devices

1st USENIX Workshop on Hot Topics in Parallelism, HotPar 2009

Volumn , Issue , 2009, Pages

  Miettinen, Antti P ^a   Hirvisalo, Vesa ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; ENERGY UTILIZATION; HAND HELD COMPUTERS; SYSTEM-ON-CHIP;

COMPILER TECHNOLOGY; DEVELOPMENT ENVIRONMENT; DEVELOPMENT PLATFORM; ENERGY EFFICIENT; ENERGY ESTIMATION; HAND HELD DEVICE; HETEROGENEOUS MPSOC; PARALLEL PROGRAM;

SOFTWARE DESIGN;

EID: 84937211089     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Symbian Symmetric Multiprocessing description, http://www.symbian.com/symbianos/os-smp.html
2. B. Lanz, Parallel SimOS: Performance and Scalability for Large System Simulation, Ph.D. Dissertation. Stanford University, Stanford, CA (2007).
3. L. T. Yang, X. Ma and F. Mueller, Cross-Platform Performance Prediction of Parallel Applications Using Partial Execution, Proc. ACM/IEEE Conf. Supercomputing (2005).
4. B. Franke, Fast cycle-approximate instruction set simulation, Proc. int. Workshop on Software & Compilers For Embedded Systems (2008).
5. Y. Neuvo, Cellular phones as embedded systems, Digest of Technical Papers, IEEE Int. Solid-State Circuits Conf. (2004) pp. 32-37.
6. K. Flautner, S. Reinhardt and T. Mudge, Automatic Performance Setting for Dynamic Voltage Scaling, Wirel. Netw., vol. 8, no. 5 (2002) pp. 507-520.
7. Maemo Software Platform, http://maemo. org/intro/platform/
8. T. Ohsawa, M. Takagi, S. Kawahara, S. Matsushita, Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities, Proc. IEEE/ACMInt. Symposium on Microarchitecture (2005) pp. 81-92
9. Nokia Energy Profiler, http://www.forum.nokia.com/main/resources/user-experience/power-management/nokia-energy-profiler/
10. J. Edler and M. D. Hill, Dinero IV Trace-Driven Uniprocessor Cache Simulator, http://pages. cs.wisc.edu/~markhill/DineroIV/
11. D. Brooks, V. Tiwari, M. Martonosi, Wattch: A Framework for Architectureal-Level Power Analysis and Optimizations, Proc. Int. Symposium on Computer Architecture (2000) pp. 83-94.
12. F. Bellard, QEMU, a fast and portable dynamic translator, Proc. USENIX Annual Technical Conf. (2005).
13. V. Hirvisalo, Using Static Program Analysis to Compile Fast Cache Simulators, Doctoral Dissertation, Helsinki University of Technology, Espoo (2004).
14. J. Larus, C. Kozyrakis, Transactional Memory, Commun. ACM, vol. 51, no. 7 (2008), pp. 80-88.
15. V. Narayanan, Network-on-Chip for 3D Architectures, Mini keynote, Int. Forum on Appliation-Specific Multi-Processor SoC (2008).