A 1,000MIPS BiCMOS microprocessor with superscalar architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1992-February, Issue , 1992, Pages 114-115

  Nishii, Osamu ^a   Hanawa, Makoto ^a   Nishimukai, Tadahiko ^a   Suzuki, Makoto ^a   Yano, Kazuo ^a   Hiraki, Mitsuru ^a   Shukuri, Shohji ^a   Nishida, Takashi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

ARITHMETIC AND LOGIC UNITS; BI-CMOS; CIRCUIT TECHNIQUES; SELF-ALIGNED; SINGLE CHIPS; SUPERSCALAR; SUPERSCALAR ARCHITECTURE;

BICMOS TECHNOLOGY;

EID: 84937077126     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1992.200438     Document Type: Conference Paper

References (6)

1. Hanawa M., et al., "On-chip Multiple Superscalar Processors with Secondary Cache Memories", ICCD'91, Oct. 1991.
2. Momose H., et al., "A Supply Voltage Design for Half pm BiCMOS Gates", Symp. VLSI Tech., June, 1989.
3. Steiss D., et al., "A 65MHz Floating-Point Coprocessor for a RISC Processor", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 94-5, Feb. 1991.
4. Suzuki M., et al., "Sense-Amplifier-Merged Comparator and Selector Scheme for BiCMOS Cache Memories", European Solid-State Circ. Conf., Sep. 1991.
5. Yano K., et al., "3.3-V BiCMOS Circuit Techniques for 250-MHz RISC Arithmetic Modules", CICC'91, May 1991.
6. Yano K., et al., "Quasi-Complementary BiCMOS for Sub-3-V Digital Circuits", Symp. VLSI Circ., Jun. 1991.