ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Volumn 2015-January, Issue January, 2014, Pages 1035-1046

  Jian, Xun ^a   Kumar, Rakesh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; ERRORS;

COMMERCIAL CHIPS; EXISTING SYSTEMS; MEMORY CHANNELS; MEMORY ENERGIES; MEMORY REGION; OVERHEAD REDUCTIONS; POWER OVERHEAD; RELIABILITY AND AVAILABILITY;

ENERGY EFFICIENCY;

EID: 84936941421     PISSN: 21674329     EISSN: 21674337     Source Type: Conference Proceeding    
DOI: 10.1109/SC.2014.89     Document Type: Conference Paper

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