Synthesis of multi-level combinational circuits for complete robust path delay fault testability

FTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing

Volumn , Issue , 1992, Pages 280-287

  Jha, N H ^a   Pomeranz, I ^b   Reddy, S M ^b   Miller, R I ^b,c  

^a PRINCETON UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

^c NCR ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; FAULT TOLERANCE; TIMING CIRCUITS;

AREA OVERHEAD; LOGIC FUNCTIONS; MULTI-OUTPUT; PATH DELAY FAULT; PATH DELAY FAULT TESTABILITY; PROGRAMMABLE LOGIC ARRAY; STUCK-AT FAULTS; SYNTHESIS RULES;

COMPUTER CIRCUITS;

EID: 84933451691     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FTCS.1992.243573     Document Type: Conference Paper

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