A High-Throughput Neural Network Accelerator

IEEE Micro

Volumn 35, Issue 3, 2015, Pages 24-32

  Chen, Tianshi ^a   Du, Zidong ^a   Sun, Ninghui ^a   Wang, Jia ^a   Wu, Chengyong ^a   Chen, Yunji ^a   Temam, Olivier ^b  

^a State Key Laboratory of Computer Architecture   (France)

^b INRIA   (France)

Author keywords

hardware accelerator; machine learning; neural network

Indexed keywords

ACCELERATION; ARTIFICIAL INTELLIGENCE; COMPUTATIONAL EFFICIENCY; DIGITAL SIGNAL PROCESSORS; EMBEDDED SYSTEMS; LEARNING SYSTEMS; MEMORY ARCHITECTURE; NEURAL NETWORKS;

ACCELERATOR ARCHITECTURES; ACCELERATOR DESIGN; BROAD APPLICATION; FIXED POINT OPERATION; HARDWARE ACCELERATORS; HETEROGENEOUS MULTI-CORES; MAIN-MEMORY ACCESS; STATE OF THE ART;

NETWORK ARCHITECTURE;

EID: 84933037461     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2015.41     Document Type: Article

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