PMOS thin gate oxide recovery upon negative bias temperature stress

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 683-684

  Akbar, Mohammad S ^a   Agostinelli, Marty ^b   Rangan, Sanjay ^b   Lau, Shing ^b   Castillo, Cesar ^b   Pae, Sangwoo ^b   Kashyap, Sridhar ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMICS; ELECTRIC FIELDS;

CHANNEL LENGTH; DYNAMIC STRESS; HIGH FREQUENCY HF; LOW FREQUENCY DYNAMICS; NEGATIVE BIAS; STRESS DURATION; THIN GATE OXIDES; UNIVERSAL BEHAVIORS;

RECOVERY;

EID: 84932177473     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315450     Document Type: Conference Paper

References (4)

1. V, Reddy et al., p. 248, 2002 IRPS
2. T. Yaraamoto et al, p.921, IEEE Trans. Elect. Dev., May 1999
3. S. Rangan and N. Mielke, accepted for 2003 IEDM
4. K. Kuhn et al., p. 73, 2002 IEDM