Cycle elimination method to construct VLSI oriented LDPC codes

IEEE Vehicular Technology Conference

Volumn 1, Issue , 2005, Pages 522-526

  Yang, Lei ^a   Liu, Hiu ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; FLOORS;

BLOCK ERROR RATES; ELIMINATION METHOD; ERROR FLOOR; IDENTITY MATRICES; NEW APPROACHES; PERFORMANCE PENALTIES; PERMUTATION MATRIX; VLSI IMPLEMENTATION;

CODES (SYMBOLS);

EID: 84931466048     PISSN: 15502252     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VETECF.2005.1557966     Document Type: Conference Paper

References (10)

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9. T. Tian, C. Jones, J. D. Villasenor and R. D. Wesel, "Construction of Irregular LDPC Codes with Low Error Floors," IEEE International Conference on Communication , vol. 5 pp. 3125-3129, May 2003.
10. D.J.C.Mackay, S.T.Wilson, and M.C.Davey, "Comparison of Constructions of Irregular Gallager Codes," IEEE Proceeding 36th Allerton Conference on Commun., Control and Comput., Sep. 1998.