Research on VHDL RTL synthesis system

Proceedings - 1st IEEE International Workshop on Electronic Design, Test and Applications, DELTA 2002

Volumn , Issue , 2002, Pages 99-103

  Zhou, Haifeng ^a   Lin, Zhenghui ^a   Cao, Wei ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; FORESTRY; FORMAL LANGUAGES; SYSTEMS ANALYSIS;

LANGUAGE LEVELS; LOOP UNROLLING; PARSER CHECKS; RESOURCE SHARING; RTL SYNTHESIS; SUB-EXPRESSIONS; VHDL DESCRIPTION; VHDL SYNTHESIS;

COMPUTATIONAL LINGUISTICS;

LANGUAGES; OPTIMIZATION; SYNTHESIS;

EID: 84931065331     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2002.994596     Document Type: Conference Paper

References (8)

1. Design Automation Standards Committee, IEEE standard for VHDL Register Transfer Level (RTL) synthesis, IEEE std1076.6-1999, New York: IEEE press, 1999.
2. Brian W. Kernighan and Rob Pike, The UNIX Programming Environment, NJ: Prentice Hall, 1984;
3. Available URL http://www.thinkage.on.ca/, 1998
4. R. Pasko, P. Schaumont, V. Derudder, et.al, A New Algorithm for Elimination of Common Subexpressions, In: IEEE Trans. on CAD . 1999, 18 (1): 58-68
5. Taewhan Kim, Noritake Yonezawa, W. S. Liu, et.al, A Scheduling Algorithm for Cond itional Resource Sharing - A Hierarchical Reduction Approach, In: IEEE Trans. on CAD. 1994, 13(4): 425~438
6. Tsing-Fa Lee, A. C. H. Wu, Y. L. Lin, et.al, A Transformation-Based Method for Loop Folding, In: IEEE Trans. on CAD. 1994, 13 (4): 439-450
7. Liang-Fang Chao, Andrea S. LaPaugh, and Edwin Hsing-Mean Sha, Rotation Scheduling: A Loop Pipelining Algorithm, In: IEEE Trans. on CAD. 1997, 16 (3): 229-238
8. Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, et al., SIS: A System for Sequential Circuit Synthesis, ERL M92/41, University of California at Berkeley , 1992.