Formal specification and verification of VHDL

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1166, Issue , 1996, Pages 310-326

  Bickford, Mark ^a   Jamsek, Damir ^a  

^a Odyssey Research Associates   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; FORMAL VERIFICATION; SPECIFICATIONS;

FORMAL SPECIFICATION AND VERIFICATION; GENERAL METHOD; STATE MACHINE;

FORMAL SPECIFICATION;

EID: 84930657331     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0031818     Document Type: Conference Paper

References (4)

1. Mark Bickford. A Formal Semantics for VHDL and its Use Towards Verifying a Large Design. Technical Report TM-92-0045, ORA Corporation, December 1992.
2. David Guaspari, Carla Marceau, and Wolfgang Polak. Formal verification of Ada programs. IEEE Transactions on Software Engineering, 16:1058-1075, September 1990.
3. John V. Guttag and James J. Horning. Larch: Languages and Tools for Formal Specification. Springer-Verlag, 1993.
4. Carlos Delgado Kloos and Peter T. Breuer (Editors). Formal Semantics for VHDL. Kluwer Academic Publishers, 1995.