The convey hybrid-core architecture

High-Performance Computing Using FPGAs

Volumn 9781461417910, Issue , 2014, Pages 431-451

  Klauer, Bernd ^a  

^a HELMUT SCHMIDT UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPUTER ARCHITECTURE;

A/D CONVERTER; ANALOGUE DOMAIN; COMPLEX COMPUTATION; CONDITION; CONVERSION TIME; DIGITAL HARDWARE; HYBRID COMPUTING; HYBRID CORES; REAL- TIME; SIGNAL-PROCESSING;

SIGNAL PROCESSING;

EID: 84929288624     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4614-1791-0_14     Document Type: Chapter

References (34)

1. G.M. Amdahl, Validity of the single processor approach to achieving large scale computing capabilities, in Proceedings of the April 18-20, 1967, Spring Joint Computer Conference, AFIPS '67 (Spring) (ACM, New York, 1967), pp. 483-485. doi:10.1145/1465482.1465560, http://doi.acm.org/10.1145/1465482.1465560
2. D. Andrews, D. Niehaus, R. Jidin, M. Finley, W. Peck, M. Frisbie, J. Ortiz, E. Komp, P. Ashenden, Programming models for hybrid fpga-cpu computational components: a missing link. IEEE Micro 24(4), 42-53 (2004). doi:10.1109/MM.2004.36, http://dx.doi.org/10.1109/ MM.2004.36
3. T.J. Callahan, J.R. Hauser, J. Wawrzynek, The Garp architecture and C compiler. Computer 33(4), 62-69 (2000). doi:http://dx.doi.org/10.1109/2.839323, http://portal.acm.org/citation. cfm?id=621455&dl=ACM&coll=portal&CFID=11111111&CFTOKEN=2222222#
4. F. Campi, M. Toma, A. Lodi, A. Cappelli, R. Canegallo, R. Guerrieri, A VLIW processor with reconfigurable instruction set for embedded applications, in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC (IEEE, New York, 2003), pp. 250-491. doi:10.1109/ISSCC.2003.1234288, http://dx.doi.org/10.1109/ ISSCC.2003.1234288
5. J.M.P. Cardoso, P.C. Diniz, M. Weinhardt, Compiling for reconfigurable computing: a survey. ACM Comput. Surv. 42(4), 1-65 (2010)
6. C. Chang, J. Wawrzynek, R.W. Brodersen, Bee2: A high-end reconfigurable computing system. IEEE Des. Test Comput. 22(2), 114-125 (2005), http://doi.ieeecomputersociety.org/10.1109/ MDT.2005.30
7. K. Compton, S. Hauck, Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34(2), 171-210 (2002), http://doi.acm.org/10.1145/508352.508353 [An excellent survey paper on reconfigurable computing]
8. Cray Inc., 411 First Avenue S., Suite 600, Seattle,WA 98104-2860 USA: Cray XD1 Datasheet, http://www.hpc.unm.edu/-tlthomas/buildout/Cray XD1 Datasheet.pdf
9. G. de Micheli, R.K. Gupta, Hardware/software co-design. IEEE Micro 85, 349-365 (1997)
10. G. Estrin, Organization of computer systems: the fixed plus variable structure computer, in Papers Presented at the May 3-5, 1960, Western Joint IRE-AIEE-ACM Computer Conference, IRE-AIEE-ACM '60 (Western) (ACM, New York, 1960), pp. 33-40. doi:10.1145/1460361.1460365, http://doi.acm.org/10.1145/1460361.1460365
11. F. Feinbube, Joint forces: the era of hybrid computer environments, in HPI Symposium @ SAP (SAP, Walldorf, 2011)
12. F. Feinbube, The future is hybrid - Developer support for accelerator-based technologies, in HPI-UCT Workshop, Capetown, 2011
13. A. George, H. Lam, G. Stitt, Novo-g: at the forefront of scalable reconfigurable supercomputing. Comput. Sci. Eng. 13, 82-86 (2011). http://doi.ieeecomputersociety.org/10.1109/MCSE. 2011.11
14. A.D. George, H. Lam, A. Lawande, C. Pascoe, G. Stitt, Novo-g: a view at the hpc crossroads for scientific computing, in Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, 12-15 July 2010, ed. by T.P. Plaks, D. Andrews, R.F. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt (CSREA Press, Las Vegas, 2010), pp. 21-30
15. J. Gray, Designing a simple fpga-optimized risc cpu and system-on-a-chip [Online] Available: http://www.dte.eis.uva.es/Docencia/PDF/soc-gr0040-001201.pdf (2000)
16. J.L. Gustafson, Reevaluating Amdahl's law. Comm. ACM 31, 532-533 (1988)
17. D. Hallmannseder, B. Klauer, Compiler Unterstützung für die dynamische Rekonfiguration eines Mikroprozessors (Compiler support for the dynamic reconfiguration of a microprocessor), in 1. Workshop Innovative Rechnertechnologien, Nanotechnologien für die IT (Helmut Schmidt Universität, Universität der Bundeswehr Hamburg, Hamburg, 2009), pp. 40-46
18. J.R. Hauser, J. Wawrzynek, Garp: a mips processor with a reconfigurable coprocessor, in Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (1997), pp. 12-21
19. Hayden Publishing, Monolithic memories announces: A revolution in logic design. Electron. Des. 26(6), 148B-148C (1978)
20. M.D. Hill, M.R. Marty, Amdahl's law in the multicore era. Computer 41(7), 33-38 (2008)
21. R. Inta, D.J. Bowman, S.M. Scott, The "chimera": an off-the-shelf cpu/gpgpu/fpga hybrid computing platform. Int. J. Reconfig. Comput. 2012, 2:2 (2012). doi:10.1155/2012/241439, http://dx.doi.org/10.1155/2012/241439
22. Intel/Altera Atom Processor E6x6C Series, Santa Clara and San Jose, http://www.altera.com/ devices/processor/intel/e6xx/proc-e6x5c.html
23. O. Khan, S. Kundu, Hardware/software codesign architecture for online testing in chip multiprocessors. IEEE Trans. Dependable Secure Comput. 8, 714-727 (2011). http://doi. ieeecomputersociety.org/10.1109/TDSC.2011.19
24. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, M. Schimmler, Breaking ciphers with copacobana - A cost-optimized parallel code breaker, in Workshop on Cryptographic Hardware and Embedded Systems - CHES 2006, Yokohama (Springer, Heidelberg, 2006), pp. 101-118
25. I. Kuon, R. Tessier, J. Rose, Fpga architecture: survey and challenges. Found. Trends Electron. Des. Automa. 2(2), 135-253 (2007). http:/dx.doi.org/10.1561/1000000005 [Modern survey of FPGA Architecture]
26. G.E. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114-117 (1965)
27. A. Niyonkuru, H.C. Zeidler, Designing a runtime reconfigurable processor for general purpose applications, in IPDPS, Santa Fe, 2004
28. R.R. Schaller, Moore's law: past, present, and future. IEEE Spectr. 34(6), 52-59 (1997). doi:10.1109/6.591665, http://dx.doi.org/10.1109/6.591665
29. T.F. Smith,M.S. Waterman, The identification of common molecular subsequences. Mol. Biol. 147, 195-197 (1981)
30. T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk, P. Cheung, Reconfigurable computing: Architectures and design methods. IEE Proc. Comput. Digit. Tech. 152(2), 193-207 (2005). http://dx.doi.org/10.1049/ip-cdt:20045086 [A recent survey paper on reconfigurable computing platforms and design with a wealth of references]
31. K.H. Tsoi,W. Luk, Axel: a heterogeneous cluster with fpgas and gpus, in FPGA, ed. by P.Y.K. Cheung, J. Wawrzynek (ACM, New York, 2010), pp. 115-124. http://doi.acm.org/10.1145/ 1723112.1723134
32. C. Ulmer, R. Hilles, D. Thompson, Reconfigurable computing aspects of the cray xd1, in Proceedings of the CUG 2005 (2005). http://www.craigulmer.com/portfolio/unlocked/050516 cug rc aspects of xd1.pdf
33. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S. Liao, C. Tseng,M. Hall, M. Lam, J. Hennessy, The suif compiler system: a parallelizing and optimizing research compiler. Technical Report, Stanford University, Stanford, CA, 1994
34. Xilinx Zynq Product Brief, San Jose, http://www.xilinx.com/support/documentation/zynq- 7000.htm