Scalable and high performance HPC architecture with optical interconnects

2014 IEEE Photonics Conference, IPC 2014

Volumn , Issue , 2014, Pages 180-181

  Cao, Zheng ^a   Proietti, Roberto ^a   Yoo, S J B ^a  

^a Davis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAT TREES; OPTICAL BACKPLANES; WAVELENGTH ROUTING;

SILICON PHOTONICS;

EID: 84921312388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPCon.2014.6995307     Document Type: Conference Paper

References (4)

1. "International Technology Roadmap for Semiconductors (ITRS), " 2012.
2. R. Yu, S. Cheung, Y. Li, K. Okamoto, R. Proietti, Y. Yin, et al., " A scalable silicon photonic chip-scale optical switch for high performance computing systems, " Optics Express, vol. 21, pp. 32655-32667, 2013/12/30 2013.
3. M. Immonen, " Development of Optical Interconnect PCBs for High Speed Electronic Systems-Fabricator's View," ECOC, 2013.
4. J. Bruck,C.-T. Ho,S. Kipnis,E. Upfal,D. Weathersby Efficient algorithms for all-to-all communications in multiport message-passing systems Parallel and Distributed Systems IEEE Transactions on 8 1143-1156 1997.