Mechanistic analytical modeling of superscalar in-order processor performance

ACM Transactions on Architecture and Code Optimization

Volumn 11, Issue 4, 2014, Pages

  Breugh, Maximilien B ^a   Eyerman, Stijn ^a   Eeckhout, Lieven ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

Cycle stacks; Functional units; Inter instruction dependences; Performance modeling; Processor design space exploration; Superscalar in order processors

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; PROGRAM COMPILERS;

CYCLE STACKS; FUNCTIONAL UNITS; INTER-INSTRUCTION DEPENDENCES; PERFORMANCE MODEL; PROCESSOR DESIGN; SUPERSCALAR;

INTEGRATED CIRCUIT DESIGN;

EID: 84921293471     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2678277     Document Type: Article

References (46)

1. D. G. Andersen, J. Franklin, M. Kaminsky, A. Phanishayee, L. Tan, and V. Vasudevan. 2009. FAWN: A fast array of wimpy nodes. In Proceedings of the International ACM Symposium on Operating Systems Principles (SOSP). 1-14.
2. ARM Holdings. 2010. Cortex-A8 Technical: Reference Manual (3p 2 ed.). ARM Holdings, Cambridge, NJ.
3. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. 2011. The gem5 simulator. Computer Architecture News 39, 2, 1-7.
4. M. Breughe, S. Eyerman, and L. Eeckhout. 2012. A mechanistic performance model for superscalar in-order processors. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 14-24.
5. M. Breughe, Z. Li, Y. Chen, S. Eyerman, O. Temam, C. Wu, and L. Eeckhout. 2011. How sensitive is processor customization to the workload's input datasets? In Proceedings of the IEEE International Symposium on Application-Specific Processors (SASP). 1-7.
6. X. E. Chen and T. M. Aamodt. 2008. Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. In Proceedings of the International Symposium on Microarchitecture (MICRO). 59-70.
7. X. E. Chen and T. M. Aamodt. 2009. A first-order fine-grained multithreaded throughput model. In Proceedings of the IEEE 15th International Symposium on High-Performance Computer Architecture (HPCA). IEEE, Los Alamitos, CA, 329-340.
8. Y. Chen, Y. Huang, L. Eeckhout, G. Fursin, L. Peng, O. Temam, and C. Wu. 2010. Evaluating iterative optimization across 1000 datasets. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). 448-459.
9. Y. Chou, B. Fahs, and S. Abraham. 2004. Microarchitecture optimizations for exploiting memory-level parallelism. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA). 76-87.
10. R. Desikan, D. Burger, and S. W. Keckler. 2001. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA). 266-277.
11. C. Dubach, T. M. Jones, and M. F. P. O'Boyle. 2007. Microarchitecture design space exploration using an architecture-centric approach. In Proceedings of the IEEE/ACM Annual International Symposium on Microarchitecture (MICRO). 262-271.
12. P. K. Dubey, G. B. Adams III, and M. J. Flynn. 1994. Instruction window size trade-offs and characterization of program parallelism. IEEE Transactions on Computers 43, 4, 431-442.
13. L. Eeckhout and K. De Bosschere. 2001. Hybrid analytical-statistical modeling for efficiently exploring architecture and workload design spaces. In Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT). 25-34.
14. L. Eeckhout, S. Nussbaum, J. E. Smith, and K. De Bosschere. 2003. Statistical simulation: Adding efficiency to the computer designer's toolbox. IEEE Micro 23, 5, 26-38.
15. D. Eklov, D. Black-Schaffer, and E. Hagersten. 2011. Fast modeling of cache contention in multicore systems. In Proceedings of the 6th International Conference on High Performance and Embedded Architecture and Compilation (HiPEAC). 147-158.
16. S. Eyerman and L. Eeckhout. 2010. Probabilistic job symbiosis modeling for SMT processor scheduling. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 91-102.
17. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. 2009. A mechanistic performance model for superscalar out-of-order processors. ACM Transactions on Computer Systems 27, 2, 42-53.
18. S. Eyerman, K. Hoste, and L. Eeckhout. 2011. Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 216-226.
19. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization (WWC).
20. A. Gutierrez, J. Pusdesris, R. G Dreslinski, T. Mudge, C. Sudanthi, C. D. Emmons, M. Hayenga, and N. Paver. 2014. Sources of error in full-system simulation. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS). 13-22.
21. G. Hamerly E. Perelman, J. Lau, and B. Calder. 2005. SimPoint 3.0: Faster and more flexible program analysis. Journal of Instruction-Level Parallelism 7, 1-28.
22. A. Hartstein and T. R. Puzak. 2002. The optimal pipeline depth for a microprocessor. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA). 7-13.
23. M. D. Hill and A. J. Smith. 1989. Evaluating associativity in CPU caches. IEEE Transactions on Computers 38, 12, 1612-1630.
24. E. Ipek, S. A. McKee, B. R. De Supinski, M. Schulz, and R. Caruana. 2006. Efficiently exploring architectural design spaces via predictive modeling. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 195-206.
25. P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. 2006a. Construction and use of linear regression models for processor performance analysis. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA). 99-108.
26. P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. 2006b. A predictive performance model for superscalar processors. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 161-170.
27. R. A. Kamin III, G. B. Adams III, and P. K. Dubey. 1994. Dynamic trace analysis for analytic modeling of superscalar performance. Performance Evaluation 19, 2-3, 259-276.
28. T. Karkhanis and J. E. Smith. 2004. A first-order superscalar processor model. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA). 338-349.
29. P. Kongetira, K. Aingaran, and K. Olukotun. 2005. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro 25, 2, 21-29.
30. B. Lee and D. Brooks. 2006. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 185-194.
31. J. Lee. 2010. A superscalar processor model for limited functional units using instruction dependencies. In Proceedings of the ISCA 25th International Conference on Computers and Their Applications (CATA). 294-299.
32. K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, and S. Reinhardt. 2008. Understanding and designing new server architectures for emerging warehouse-computing environments. In Proceedings of the International Symposium on Computer Architecture (ISCA). 315-326.
33. G. Mariani, G. Palermo, V. Zaccaria, and C. Silvano. 2013. Design-space exploration and runtime resource management for multicores. ACM Transactions on Embedded Computing Systems 13, 2, Article 20.
34. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. 1970. Evaluation techniques for storage hierarchies. IBM Systems Journal 9, 2, 78-117.
35. P. Michaud, A. Seznec, and S. Jourdan. 1999. Exploring instruction-fetch bandwidth requirement in wideissue superscalar processors. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT). 2-10.
36. D. B. Noonburg and J. P. Shen. 1994. Theoretical modeling of superscalar processor performance. In Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO). 52-62.
37. D. B. Noonburg and J. P. Shen. 1997. A framework for statistical modeling of superscalar processor performance. In Proceedings of the 3rd International Symposium on High-Performance Computer Architecture (HPCA). 298-309.
38. M. Oskin, F. T. Chong, and M. Farrens. 2000. HLS: Combining statistical and symbolic simulation to guide microprocessor design. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA). 71-82.
39. E. Ould-Ahmed-Vall, J. Woodlee, C. Yount, K. A. Doshi, and S. Abraham. 2007. Using model trees for computer architecture performance analysis of software applications. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 116-125.
40. V. J. Reddi, B. C. Lee, T. Chilimbi, and K. Vaid. 2010. Web search using mobile cores: Quantifying and mitigating the price of efficiency. In Proceedings of the International Symposium on Computer Architecture (ISCA). 26-36.
41. T. M. Taha and D. S. Wills. 2008. An instruction throughput model of superscalar processors. IEEE Transactions on Computers 57, 3, 389-403.
42. Texas Instruments Incorporated. 2014. AM335x Sitara Processors: Technical Reference Manual. Texas Instruments Incorporated, Dallas, TX.
43. M. Van Biesbrouck, T. Sherwood, and B. Calder. 2004. A co-phase matrix to guide simultaneous multithreading simulation. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS). 45-56.
44. K. Van Craeynest and L. Eeckhout. 2011. The multi-program performance model: Debunking current practice in multi-core simulation. In Proceedings of the 2011 IEEE International Symposium on Workload Characterization (IISWC). IEEE, Los Alamitos, CA, 26-37.
45. K. Van Craeynest, A. Jaleel, L. Eeckhout, P. Narvaez, and J. Emer. 2012. Scheduling heterogeneous multicores through performance impact estimation (pie). In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA). 213-224.
46. Y. Zhu, W. Wong, and Ş. Andrei. 2005. An integrated performance and power model for superscalar processor designs. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference (ASP-DAC). 948-951.