The Correct Equivalent Box Representation for the Buried Layer of BC MOSFET's in Terms of the Implantation Parameters

IEEE Electron Device Letters

Volumn 8, Issue 10, 1987, Pages 457-459

  Karmalkar, S ^a   Bhat, K N ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84916447709     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26693     Document Type: Article

References (7)

1. S. M. Sze, Ed., VLSI Technology. New York: McGraw-Hill, 1983.
2. J. T. S. Huang and G. W. Taylor, “Modelling of an ion-implanted silicon-gate depletion mode IGFET,” IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 995–1001, Nov. 1975.
3. R. A. Haken, “Analysis of the deep depletion MOSFET and the use of d.c. characteristics for determining bulk channel charge device parameters,” Solid-State Electron., vol. 21, pp. 753–761, May 1978.
4. M. H. White, F. B. Wiele, and J. P. Lambot, “High accuracy MOS models for computer-aided design,” IEEE Trans. Electron Devices, vol. ED-27, pp. 899–906, May 1980.
5. Y. A. El-Mansy, “Analysis and Characterization of the depletion mode IGFET,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 331–340, June 1980.
6. A. B. Bhattacharya et al. “On-line extraction of model parameters of a long buried-channel MOSFET.” IEEE Trans. Electron Devices, vol. ED-32, no. 3, pp. 545–550, Mar. 1985.
7. G. W. Taylor, P. K. Chatterjee, and H. H. Chao, “A device model for buried-channel CCDs and MOSFETs for Gaussian impurity profiles,” IEEE Trans. Electron Devices, vol. ED-27, no. 1, pp. 199–208, Jan. 1980.