Threshold voltage tuning for 10nm and beyond CMOS integration

Solid State Technology

Volumn 57, Issue 7, 2014, Pages 23-25

  Yoshida, Naomi ^a   Han, Keping ^a   Beach, Matthew ^a   Lu, Xinliang ^a   Hung, Raymond ^a   Chen, Hao ^a   Tang, Wei ^a   Lei, Yu ^a   Zhou, Jing ^a   Jin, Miao ^a   Xu, Kun ^a   Phatak, Anup ^a   Sun, Shiyu ^a   Hassan, Sajjad ^a   Gandikota, Srinivas ^a   Chang, Chorng Ping ^a   Bran, Adam ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION; CHARGE COUPLED DEVICES; CMOS INTEGRATED CIRCUITS; HIGH-K DIELECTRIC; ION IMPLANTATION; IONS; METALS; MOS DEVICES; OXIDE SEMICONDUCTORS; THRESHOLD VOLTAGE;

CURRENT VOLTAGE MEASUREMENT; HIGH FREQUENCY CAPACITANCE; METAL COMPOSITION; METAL DEPOSITION; METAL-OXIDE-SEMICONDUCTOR CAPACITORS; NITROGEN ION IMPLANTATIONS; SINGLE DAMASCENE STRUCTURES; THRESHOLD VOLTAGE TUNING;

CAPACITANCE;

EID: 84913588250     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (5)

1. C. Auth et al., VLSI Tech. Sym. Dig., p. 131, (2012)
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3. ITRS Roadmap 2011 Edition
4. N. Yoshida, et al., VLSI Tech. Sym. Dig., p. 81, (2012)
5. A. Veloso, et al., VLSI Tech. Sym. Dig., p. 33, (2012)