Verilog-A compact model for oxide-based resistive random access memory (RRAM)

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2014, Pages 41-44

  Jiang, Zizhen ^a   Yu, Shimeng ^b   Wu, Yi ^c   Engel, Jesse H ^a   Guan, Ximeng ^d   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

^c ORACLE CORPORATION   (United States)

^d IBM RESEARCH   (United States)

Author keywords

Compact model; RRAM; variations; Verilog A

Indexed keywords

RRAM;

COMPACT MODEL; PARAMETER FITTING; PULSED OPERATION; RANDOM VARIABILITY; REAL TIME; RESISTIVE RANDOM ACCESS MEMORY (RRAM); VARIATIONS; VERILOG-A;

FIELD EFFECT TRANSISTORS;

EID: 84908672775     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2014.6931558     Document Type: Conference Paper

References (7)

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