Simulation speedup for DEVS models by composition-based compilation

Simulation Series

Volumn 35, Issue 3, 2003, Pages 395-400

  Bok Lee, Wan ^a   Gon Kim, Tag ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

DEVS formalism; Performance evaluation; Simulation speedup

Indexed keywords

ALGORITHMS;

COMMUNICATION PATH; COMPILED SIMULATION; COUPLING PROPERTIES; DEVS FORMALISM; MODELING AND SIMULATION METHODOLOGIES; PERFORMANCE EVALUATION; SIMULATION SPEED-UP; TRANSFORMATION METHODS;

DISCRETE EVENT SIMULATION;

EID: 84907917093     PISSN: 07359276     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. R. Sargent, "Hierarchical modeling for discrete event simulation (panel)" In Proceedings of the 1993 Winter Simulation Conference, p569.
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4. Myung S. Ahn and Tag G. Kim. "A Framework for Hybrid Modeling/Simulation of Discrete Event Systems," AIS'94, pp. 199-205, Dec. 1994, Gainesville, FL.
5. Y. G. Kim and T. G. Kim, "Optimization of Model Execution Time in the DEVSim-H- Environment", in Proc. of 1997 European Simulation Symposium, pp.2 15-219, Oct. 1997, Passau, Germany.
6. D. M. Lewis, "A hierarchical compiled code even- driven logic simulator," IEEE Transactions on Computer-Aided Design. vol. 10, no. 6, pp.726-737. 1991.
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8. Ki Jung Hong and Tag Gon Kim, "DEVSIF Relational Algebraic DEVS Intermediate Format," Proceedings of AIS'2000, Tucson, Arizona, U.S.A., 2000.
9. T. G. Kim, and S. B. Park, "The DEVS Formalism: Hierarchical Modular Systems Specification in C++" In Proceedings of the 1992 European Simulation Multiconference, pp.152-156, 1992.
10. Supplements to Carrier Sense Multiple Access with Collision Detection, Institue of Electrical and Electronics Engineers Inc., 1988.