A 0.35μm BiCMOS Process with Selective Epitaxial SiGe Bipolar Transistors

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 436-439

  Kuhn, R ^a   Decoutere, S ^a   Caymax, M ^a   Vleugels, F ^a   Verschooten, E ^a   Loo, R ^a   Loheac, J L ^b  

^a IMEC   (Belgium)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; SEMICONDUCTING SILICON; SILICON ALLOYS;

BI-CMOS PROCESS; GROWTH PROCESS; LOCAL LOADING; TEMPERATURE COMPENSATION;

LOADING;

EID: 84907905199     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. S. Ito, T. Nakamura and S. Nishikawa, "Pattern dependence in selective epitaxial SiGe growth using reduced-pressure chemical vapor depositidn", J. Appl. Phys., Vol. 78, p. 2716, 1995.
2. W. De Boer. D. Terpstra and R. Dekker, "Loading effects during low-temperature SEG of Si and SiGe", Mat. Res. Soc. Symp. Proc. Vol. 533, p. 315, 1998.