Optimization of critical ion implantation steps in 0.18 μm CMOS technology

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 92-95

  Bourenkov, A ^a   Wittl, J ^a   Schwalke, U ^b   Lorenz, J ^a   Ryssel, H ^a,c  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

^b SIEMENS AG   (Germany)

^c UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; IONS;

CMOS TECHNOLOGY; CMOS TRANSISTORS; COUPLED PROCESS; DEVICE SIMULATIONS; DRIVE CURRENTS; EFFECTIVE GATE LENGTH; OVERLAP CAPACITANCE; SWITCHING SPEED;

ION IMPLANTATION;

EID: 84907904392     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Rodder et al., IEDM-96 Techn. Digest, pp.563-566.
2. U. Schwalke et al., ESSDERC'97 Proceedings, Stuttgart; 1997, pp. 220-223.
3. M. ROdder et al., VLSI Technology Systems and Applications, 1999, pp. 29-33.