A complementary BiCMOS technology for low power wireless telecommunication applications

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 444-447

  Ammo, Hiroaki ^a   Ejiri, Hirokazu ^a   Kanematsu, S ^a   Kikuchi, Shigeru ^a   Yano, Motoyasu ^a   Miwa, Hiroyuki ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

BIPOLAR DEVICE; CMOS DEVICES; CMOS TRANSISTORS; LOW POWER WIRELESS; N-P-N TRANSISTORS; REDUCING PROCESS; VERTICAL PNP; WIRELESS TELECOMMUNICATIONS;

BICMOS TECHNOLOGY;

EID: 84907899110     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. H Miwa et al. "A complementary bipolar technology for low cost and high performance mixed analog/digital applications", Proc. IEEE 1996 BCTTvl, Minneapolis, pp. 185-188.
2. G Oga et al. "High speed ECL to CMOS interface and output buffer combining bipolar with CMOS", Proc. IEEJ 1999 Analog VLSI Workshop, Taipei.