Back-bias enhanced source-side injection in 0.25um embedded flash memories

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 608-611

  Van Houdt, J ^a   Verheyen, P ^a   Frisson, F ^a   Wellekens, D ^a   Lorenzini, M ^a   Maes, H E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; ELECTRON INJECTION; HOT ELECTRONS; IMPACT IONIZATION; SEMICONDUCTOR STORAGE;

BITLINE VOLTAGES; DEEP SUB-MICRON TECHNOLOGY; EMBEDDED FLASH MEMORY; INJECTION BARRIERS; NEGATIVE VOLTAGE; SECONDARY IMPACT IONIZATIONS; SEMICONDUCTOR MEMORY; SOURCE-SIDE INJECTION;

FLASH MEMORY;

EID: 84907894840     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. R. Heinrich, W. Heinrigs, G. Tempel, J. Winnerl, Th. Zettler, "A O.511m CMOS technology for multifunctional applications with embedded FN-Flash memory and linear R and C modules", IEDM Tech. Dig. 1993, pp.445-448.
3. J. Van Houdt, G. Groeseneken, H.E. Maes, "Transistor structure for erasable and programmable semiconductor memory devices", US patent no. 5,583,811, 1996.
4. J.D. Bude, A. Frommer, M.R. Pinto, G.R. Weber, "EEPROMlFlash Sub 3.0V Drain-Source Bias Hot Carrier Writing", IEDM Tech. Dig. 1995, pp. 989-991.
5. W. Quade, M. Rudan, E. Scholl, "Hydrodynamic simulation of impactionization effects in p-n junctions", IEEE Trans. Computer-Aided Design, voL 10, No.10, 1991, pp.1287-1294.