Ultra-Shallow extensions for industrial 0.15 μm CMOS technology fabricated using Plasma Doping

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 392-395

  Lenoble, D ^a   Alieu, J ^b   Grouillet, A ^b   Haond, M ^b   Felch, S B ^c   Goeckner, M J ^c   Fang, Z ^c  

^a ORANGE LABS   (France)

^b CNETIST Microelectronics ^*  (France)

^c Varian Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; GATE DIELECTRICS; GATES (TRANSISTOR); SEMICONDUCTOR DOPING;

CHANNEL CONTROL; CMOS FABRICATION; CMOS TECHNOLOGY; DEVICE CHARACTERISTICS; GATE OXIDE RELIABILITY; LATERAL DIFFUSION; LIGHTLY DOPED DRAINS; PLASMA DOPING;

FABRICATION;

EID: 84907894834     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K. Goto, et al, IEDM Tech. Dig., 1998
2. D. Lenoble, et al, to be published in Ion Implant Technology proceedings
3. R. B. Fair, IEEE Trans. on Electron Devices, 37 (10), October (1990)