Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2014, Pages

  Chen, Hong Yu ^a,b   Gao, Bin ^a   Li, Haitong ^a   Liu, Rui ^a   Huang, Peng ^a   Chen, Zhe ^a   Chen, Bing ^a   Zhang, Feifei ^a   Zhao, Liang ^b   Jiang, Zizhen ^b   Liu, Lifeng ^a   Liu, Xiaoyan ^a   Kang, Jinfeng ^a   Yu, Shimeng ^c   Nishi, Yoshio ^b   Wong, H S Philip ^b  

^a PEKING UNIVERSITY   (China)

^b STANFORD UNIVERSITY   (United States)

^c ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATION; VLSI CIRCUITS;

2D ARRAYS; 3D ARRAYS; CELL LOCATION; DOUBLE SIDED; HIGH SPEED; WORST-CASE ANALYSIS;

RRAM;

EID: 84907708572     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2014.6894434     Document Type: Conference Paper

References (9)

1. I. G. Baek, et al., IEDM 2011, p. 737.
2. W. C. Chien, et al., VLSI 2012, p. 153.
3. H.-Y. Chen, et al., IEDM 2012, p. 497.
4. S. Yu, et al., VLSI 2013, p. 158.
5. Y. Deng, et al., IEDM 2013, p. 629.
6. T. Diokh, et al., IRPS 2013, p. 5E.4.1.
7. H. Li, et al., EDL, 35, 2, p. 21, 2014.
8. S. Yu, et al., APL 98, 103514, 2001.
9. X. P. Wang, et al., IEDM 2012, p. 493.