메뉴 건너뛰기




Volumn , Issue , 1997, Pages 260-263

A 0.5 um flash technology suitable for low voltage embedded applications

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE;

EID: 84907533457     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194415     Document Type: Conference Paper
Times cited : (2)

References (4)
  • 1
    • 4243592160 scopus 로고
    • A novel cell structure suitable for A 3 volt operation, sector erase flash memory
    • H. Onoda, et al., A Novel Cell Structure suitable for A 3 Volt Operation, Sector Erase Flash Memory, in IEDM Tech. Digest, 1992, pp.92.
    • (1992) IEDM Tech. Digest , pp. 92
    • Onoda, H.1
  • 2
    • 0027816546 scopus 로고
    • A high capacitive-coupling ratio (HiCR) cell for A 3V-only 64 Mbit and future flash memory
    • Yosiaki S. Hisamune, et al., A High Capacitive-Coupling Ratio (HiCR) Cell for A 3V-only 64 Mbit and future Flash Memory, in IEDM Tech. Digest, 1993, pp.19.
    • (1993) IEDM Tech. Digest , pp. 19
    • Hisamune, Y.S.1
  • 3
    • 0027851236 scopus 로고
    • A 0.5 um CMOS technology for mutifunctional applications with embedded FN-flash memory and linear R and C modules
    • Roland Heinrich, et al., A 0.5 um CMOS Technology for Mutifunctional Applications with Embedded FN-Flash Memory and Linear R and C Modules, in IEDM Tech. Digest, 1993, pp.445.
    • (1993) IEDM Tech. Digest , pp. 445
    • Heinrich, R.1
  • 4
    • 0028419935 scopus 로고
    • Memory array architecture and decoding scheme for 3 v only sector erasable DINOR flash memory
    • Apr.
    • Shin-ichi Kobayashi, et al., Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory, in IEEE J. Solid-State Circuit, vol. 29, no. 4, Apr. 1994, pp.454.
    • (1994) IEEE J. Solid-State Circuit , vol.29 , Issue.4 , pp. 454
    • Kobayashi, S.-I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.