A 0.5 um flash technology suitable for low voltage embedded applications

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 260-263

  Yeh, J K ^a   Su, H D ^a   Lin, Y F ^a   Shieh, C D ^a   Kuo, D S ^a   Liang, M S ^a   Tao, G Q ^b   List, F J ^b   Shi, L ^b   Colclaser, R ^b   Tandan, N ^b   Chen, K ^b   Chen, M ^b   Van Gorkum, A ^b  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE;

EMBEDDED APPLICATION; FLASH MEMORY CELL; FLASH TECHNOLOGY; FOWLER-NORDHEIM TUNNELING; LOW SUPPLY VOLTAGES; LOW-POWER CONSUMPTION; PORTABLE ELECTRONICS; PROGRAMMING TIME;

FLASH MEMORY;

EID: 84907533457     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194415     Document Type: Conference Paper

References (4)

1. H. Onoda, et al., A Novel Cell Structure suitable for A 3 Volt Operation, Sector Erase Flash Memory, in IEDM Tech. Digest, 1992, pp.92.
2. Yosiaki S. Hisamune, et al., A High Capacitive-Coupling Ratio (HiCR) Cell for A 3V-only 64 Mbit and future Flash Memory, in IEDM Tech. Digest, 1993, pp.19.
3. Roland Heinrich, et al., A 0.5 um CMOS Technology for Mutifunctional Applications with Embedded FN-Flash Memory and Linear R and C Modules, in IEDM Tech. Digest, 1993, pp.445.
4. Shin-ichi Kobayashi, et al., Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory, in IEEE J. Solid-State Circuit, vol. 29, no. 4, Apr. 1994, pp.454.