SiGe gate for highly performant 0.15/0.18μm CMOS technology

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 216-219

  Skotnicki, T ^a   Bouillon, P ^a   Gwoziecki, R ^a   Halimaoui, A ^a   Mourrain, C ^a   Sagnes, I ^a   Regolini, J L ^a   Jouber, O ^b   Paoli, M ^a   Schiavone, P ^a  

^a ORANGE LABS   (France)

^b Inst Mat Nantes UMR 110 C   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GERMANIUM; SILICON; TRANSCONDUCTANCE;

CHANNEL DEVICE; CHANNEL DOPINGS; CMOS PROCESSS; CMOS TECHNOLOGY; GATE LENGTH; GATE MATERIALS; RESEARCH LABS; TRANSISTOR LEVEL;

SILICON ALLOYS;

EID: 84907527860     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194404     Document Type: Conference Paper

References (8)

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5. T. Ushiki et al., IEDM'96 Tech. Dig., pp. 117-120.
6. T. Skotnicki, ESSDERC'96 Proceedings, pp. 505-514.
7. C. Salm et al., ESSDERC'96 Proceedings, pp. 601-604.
8. L. Risch et al., ESSDERC'95. Proceedings, pp. 101-104.