Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 587-590

  Wang, Pei Hua ^a   Lee, Brian ^a   Han, Gus ^a   Rouse, Richard ^b   Hurat, Philippe ^b   Verghese, Nishath ^b  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b Clear Shape Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE; INTEGRATED CIRCUITS; STRUCTURAL DESIGN;

DELAY CALCULATION; NARROW-WIDTH EFFECTS; PARAMETRIC FAILURE; PATTERN VARIATION; RING OSCILLATOR STRUCTURES; SIMULATION METHODOLOGY; SYSTEMATIC VARIATION; WAVELENGTH OF LIGHT;

INTEGRATED CIRCUIT DESIGN;

EID: 84906725009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405800     Document Type: Conference Paper

References (5)

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3. S. B. Chiah, X. Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects", Nanotech 2003, Vol. 2, Cambridge, MA, 2003, pp. 338-341.
4. K-W. Su, Y-M. Sheu, C-K. Lin, S-J. Yang, W-J. Liang, X. Xi, CS. Chiang, J-K. Her, Y-T. Chia, C. H. Diaz, and C. Hu, "A Scalable Model for STI Mechanical Stress Effects on Layout Dependence of MOS Electrical Characteristics", IEEE 2003 Custom Integrated Circuits Conference, Sept. 2003, pp. 245-248.
5. D. Tsien, C. K Wang , Y. Ran, P. Hurat, N. Verghese, "Contextspecific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability" SPIE 2007