TBPoint: Reducing simulation time for large-scale GPGPU kernels

Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS

Volumn , Issue , 2014, Pages 437-446

  Huang, Jen Cheng ^a   Nai, Lifeng ^a   Kim, Hyesoon ^b   Lee, Hsien Hsin S ^a  

^a Georgia Institute of Techonology   (United States)

^b Georgia Institute of Technology   (United States)

Author keywords

GPGPU; performance modeling; sampling; simulation

Indexed keywords

DISTRIBUTED PARAMETER NETWORKS; RANDOM ERRORS; SAMPLING;

ARCHITECTURE SIMULATION; CYCLE-LEVEL SIMULATION; GPGPU; PERFORMANCE MODEL; SAMPLING ERRORS; SIMULATION; SIMULATION TIME; TIMING SIMULATIONS;

PROGRAM PROCESSORS;

EID: 84906709211     PISSN: 15302075     EISSN: 23321237     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2014.53     Document Type: Conference Paper

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