Framework for economical error recovery in embedded cores

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014

Volumn , Issue , 2014, Pages 146-153

  Upasani, Gaurang ^a   Vera, Xavier ^b   Gonzalez, Antonio ^a,b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTICS; BUDGET CONTROL; ERROR DETECTION; TRANSISTORS;

CHIP MULTI-PROCESSORS (CMPS); EXPONENTIAL GROWTH RATES; LOWER VOLTAGES; ON-CHIP TRANSISTORS; SCALABLE ARCHITECTURES; SHRINKING FEATURE SIZES; TRANSIENT ERRORS; WAVE DETECTORS;

EMBEDDED SYSTEMS;

EID: 84906665953     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2014.6873687     Document Type: Conference Paper

References (24)

1. R. E. Ahmed, R. C. Frazier, and R N. Marinos. Cache-aided rollback error recovery (carer) algorithm for shared-memory multiprocessor systems. In 20th International Symposium Fault-Tolerant Computing, 1990. FTCS-20., pages 82-88. IEEE, 1990.
2. ARM. ARM Cortex A5 Technical Reference Manual. ARM. http://infocenter. arm.com/help/topic/com.arm.doc.ddi0433b/DDI0433B-cortex-a5-r0pl-trm.pdf.
3. ARM. ARM11 Technical Reference Manual. ARM. http://infocenter.arm.com/ help/topic/com.arm.doc.ddi0360e/DDI0360E-armll-mpcore-rlpO-trm.pdf
4. T. M. Austin. DIVA: a reliable substrate for deep submicron microarchitecture design. In Proceedings of International Symposium on Microarchitecture (MICRO), 1999.
5. W. Bartlett and L. Spainhower. Commercial fault tolerance: A tale of two systems. IEEE Transactions on Dependable and Secure Computing, , l(l): 87-96, 2004.
6. R. Baumann. Silicon amnesia: a tutorial on radiation induced soft errors. In IRPS, 2001.
7. D. Bernick, B. Bruckert, R D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. Nonstop® advanced architecture. In Proceedings of IEEE International Conference on DSN, 2005., pages 12-21.
8. J. Blome, S. Mahlke, D. Bradley, and K. Flautner. A microarchitectural analysis of soft error propagation in a production-level embedded microprocessor. In In Proceedings of the First Workshop on Architecture Reliability, 2005.
9. D. Burger and T. M. Austin. The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News, 25(3): 13-25, 1997.
10. A. Dixit and A. Wood. The impact of new technology on soft error rates. In Proceedings of IRPS, 2011.
11. B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, and S. Garverick. An efficient bics design for seus detection and correction in semiconductor memories. In Proceedings of DATE-Volume 1, pages 592-597, 2005.
12. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE WWC-4. 2001 , pages 3-14., 2001.
13. M. Hammig. Nuclear radiation detection via the detection of pliable microstructures. In Proceedings of Nuclear Instruments and Methods in Physics Research, pages 278-281, Los Alamitos, CA, USA, 1999.
14. E. HANNAH. Cosmic ray detectors for integrated circuit chips. United States Patent Number 7309866B2, December 2007.
15. S. S. Mukherjee. Architecture Design for Soft Errors. 1st edition, 2009.
16. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt. Detailed design and evaluation of redundant multithreading alternatives. In Proceedings of International Symposium on Computer Architecture (ISCA), 2002.
17. A. Narsale and M. C. Huang. Variation-tolerant hierarchical voltage monitoring circuit for soft error detection. IEEE ISQED, 2009.
18. G. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. August. SWIFT: Software implemented fault tolerance. In Proceedings of the International Symposium on Code Generation and Optimization (CGO), 2005.
19. S. D. Rodgers and L. O. Smith. Method and apparatus for processing events in a multithreaded processor, Feb. 15 2005. US Patent 6, 857, 064.
20. E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of International Symposium on Fault-Tolerant Computing (FTC), page 84, 1999.
21. L. Spainhower and T. A. Gregg. IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective. IBM Journal of Research and Development, 43(5/6): 863-873, 1999.
22. K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream processors: improving both performance and fault tolerance. In Proceedings of the 33th International Symposium on Microarchitecture (MICRO), 2000.
23. G. Upasani, X. Vera, and A. Gonzalez. Setting an error detection infrastructure with low cost acoustic wave detectors. In Proceedings of the ISCA, 2012.
24. G. Upasani, X. Vera, and A. Gonzalez. Reducing due-fit of caches by exploiting acoustic wave detectors for error recovery. In IOLTS, pages 85-91, 2013.