메뉴 건너뛰기




Volumn , Issue , 2014, Pages 85-96

ArchRanker: A ranking approach to design space exploration

Author keywords

[No Author keywords available]

Indexed keywords

REGRESSION ANALYSIS;

EID: 84905495779     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2014.6853198     Document Type: Conference Paper
Times cited : (33)

References (45)
  • 1
    • 77954986440 scopus 로고    scopus 로고
    • Energyperformance tradeoffs in processor architecture and circuit design: A marginal cost analysis
    • O. Azizi, A. Mahesri, B. C. Lee, S. J. Patel, and M. Horowitz, "Energyperformance tradeoffs in processor architecture and circuit design: A marginal cost analysis", in ISCA-37, 2010.
    • (2010) ISCA-37
    • Azizi, O.1    Mahesri, A.2    Lee, B.C.3    Patel, S.J.4    Horowitz, M.5
  • 2
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • D. Brooks, V. Tiwari and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations", in ISCA-27, 2000.
    • (2000) ISCA-27
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 3
    • 21244474546 scopus 로고    scopus 로고
    • Predicting inter-thread cache contention on a chip multi-processor Architecture
    • D. Chandra, F. Guo, S. Kim, and Y. Solihin, "Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture", in HPCA-11, 2005.
    • (2005) HPCA-11
    • Chandra, D.1    Guo, F.2    Kim, S.3    Solihin, Y.4
  • 4
    • 64949101685 scopus 로고    scopus 로고
    • A first-order fine-grained multithreaded throughput model
    • X. E. Chen and T. M. Aamodt, "A first-order fine-grained multithreaded throughput model", in HPCA-15, 2009.
    • (2009) HPCA-15
    • Chen, X.E.1    Aamodt, T.M.2
  • 5
    • 84861811396 scopus 로고    scopus 로고
    • Modeling cache contention and throughput of multiprogrammed manycore processors
    • X. E. Chen and T. M. Aamodt, "Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors", IEEE Transactions on Computers 61(7), 2012.
    • IEEE Transactions on Computers , vol.61 , Issue.7 , pp. 2012
    • Chen, X.E.1    Aamodt, T.M.2
  • 6
    • 47349128966 scopus 로고    scopus 로고
    • Microarchitectural design space exploration using an architecture-centric approach
    • C. Dubach, T. M. Jones, and M. F. P. OBoyle, "Microarchitectural Design Space Exploration Using an Architecture-Centric Approach", in MICRO-40, 2007.
    • (2007) MICRO-40
    • Dubach, C.1    Jones, T.M.2    Oboyle, M.F.P.3
  • 7
    • 63349088199 scopus 로고    scopus 로고
    • Exploring and predicting the architecture/optimising compiler co-design space
    • C. Dubach, T. M. Jones, and M. F. P. OBoyle, "Exploring and predicting the architecture/optimising compiler co-design space", in CASES08, 2008.
    • (2008) CASES08
    • Dubach, C.1    Jones, T.M.2    Oboyle, M.F.P.3
  • 8
    • 79951697270 scopus 로고    scopus 로고
    • A predictive model for dynamic microarchitectural adaptivity control
    • C. Dubach, T. M. Jones, E. V. Bonilla, and M. F. P. OBoyle, "A predictive model for dynamic microarchitectural adaptivity control", in MICRO-43, 2010.
    • (2010) MICRO-43
    • Dubach, C.1    Jones, T.M.2    Bonilla, E.V.3    Oboyle, M.F.P.4
  • 9
    • 4644258856 scopus 로고    scopus 로고
    • Control flow modeling in statistical simulation for accurate and efficient processor design studies
    • L. Eeckhout, R. H. Bell Jr., B. Stougie, K. D. Bosschere, and L. K. John, "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies", in ISCA-31, 2004.
    • (2004) ISCA-31
    • Eeckhout, L.1    Bell Jr., R.H.2    Stougie, B.3    Bosschere, K.D.4    John, L.K.5
  • 13
    • 52949107219 scopus 로고    scopus 로고
    • Statistical simulation of chip multiprocessors running multi-program workloads
    • D. Genbrugge and L. Eeckhout, "Statistical simulation of chip multiprocessors running multi-program workloads", in ICCD-25, 2007.
    • (2007) ICCD-25
    • Genbrugge, D.1    Eeckhout, L.2
  • 14
    • 74549142310 scopus 로고    scopus 로고
    • Chip multiprocessor design space exploration through statistical simulation
    • D. Genbrugge and L. Eeckhout, "Chip Multiprocessor Design Space Exploration through Statistical Simulation", IEEE Transactions on Computers 58(12), 2009.
    • (2009) IEEE Transactions on Computers , vol.58 , Issue.12
    • Genbrugge, D.1    Eeckhout, L.2
  • 15
    • 84881073232 scopus 로고    scopus 로고
    • Effective and efficient microprocessor design space exploration Using unlabeled design configurations
    • Q. Guo, T. Chen, Y. Chen, Z.-H. Zhou,W. Hu, and Z. Xu, "Effective and Efficient Microprocessor Design Space Exploration Using Unlabeled Design Configurations," in IJCAI11, 2011.
    • (2011) IJCAI11
    • Guo, Q.1    Chen, T.2    Chen, Y.3    Zhou, Z.-H.4    Hu, W.5    Xu, Z.6
  • 18
    • 34547417098 scopus 로고    scopus 로고
    • Efficiently exploring architectural design spaces via predictive modeling
    • E. Ipek, S. A. McKee, B. de Supinski, M. Schulz, and R. Caruana, "Efficiently exploring architectural design spaces via predictive modeling", in ASPLOS-12, 2006.
    • (2006) ASPLOS-12
    • Ipek, E.1    McKee, S.A.2    De Supinski, B.3    Schulz, M.4    Caruana, R.5
  • 20
    • 0029700388 scopus 로고    scopus 로고
    • Representative traces for processor models with infinite cache
    • V. S. Iyengar, L. H. Trevillyan, and P. Bose, "Representative Traces for Processor Models with Infinite Cache", in HPCA-2, 1996.
    • (1996) HPCA-2
    • Iyengar, V.S.1    Trevillyan, L.H.2    Bose, P.3
  • 21
    • 33748863916 scopus 로고    scopus 로고
    • Construction and use of linear regression models for processor performance analysis
    • P. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "Construction and use of linear regression models for processor performance analysis", in HPCA-12, 2006.
    • (2006) HPCA-12
    • Joseph, P.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 22
    • 34548333834 scopus 로고    scopus 로고
    • A predictive performance model for superscalar processors
    • P. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "A Predictive Performance Model for Superscalar Processors", in MICRO-39, 2006
    • (2006) MICRO-39
    • Joseph, P.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 23
    • 4644299010 scopus 로고    scopus 로고
    • A first-order superscalar processor model
    • T. S. Karkhanis and J. E. Smith, "A First-Order Superscalar Processor Model", in ISCA-31, 2004.
    • (2004) ISCA-31
    • Karkhanis, T.S.1    Smith, J.E.2
  • 24
    • 47849123249 scopus 로고    scopus 로고
    • Using predictive modeling for cross-program design space exploration in multicore systems
    • S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra, "Using Predictive Modeling for Cross-Program Design Space Exploration in Multicore Systems", in PACT-16, 2007.
    • (2007) PACT-16
    • Khan, S.1    Xekalakis, P.2    Cavazos, J.3    Cintra, M.4
  • 25
    • 34547288276 scopus 로고    scopus 로고
    • Accurate and efficient regression modeling for microarchitectural performance and power prediction
    • B. C. Lee and D. Brooks, "Accurate and efficient regression modeling for microarchitectural performance and power prediction", in ASPLOS-12, 2006.
    • (2006) ASPLOS-12
    • Lee, B.C.1    Brooks, D.2
  • 26
    • 34547702258 scopus 로고    scopus 로고
    • Illustrative design space studies with microarchitectural regression models
    • B. C. Lee and D. Brooks, "Illustrative design space studies with microarchitectural regression models", in HPCA-13, 2007.
    • (2007) HPCA-13
    • Lee, B.C.1    Brooks, D.2
  • 28
    • 66749185800 scopus 로고    scopus 로고
    • CPR: Composable performance regression for scalable multiprocessor models
    • B. C. Lee, J. Collins, H. Wang, and D. Brooks, "CPR: Composable performance regression for scalable multiprocessor models", in MICRO-41, 2008.
    • (2008) MICRO-41
    • Lee, B.C.1    Collins, J.2    Wang, H.3    Brooks, D.4
  • 30
    • 84864831082 scopus 로고    scopus 로고
    • A first-order mechanistic model for architectural vulnerability factor
    • A. A. Nair, S. Eyerman, L. Eeckhout, and L. K. John, "A first-order mechanistic model for architectural vulnerability factor", in ISCA-39, 2012.
    • (2012) ISCA-39
    • Nair, A.A.1    Eyerman, S.2    Eeckhout, L.3    John, L.K.4
  • 31
    • 62349141993 scopus 로고    scopus 로고
    • Simulation points for SPEC CPU 2006
    • A. A. Nair and L. K. John, "Simulation points for SPEC CPU 2006", in ICCD-26, 2008.
    • (2008) ICCD-26
    • Nair, A.A.1    John, L.K.2
  • 32
    • 85016676932 scopus 로고
    • Theoretical modeling of superscalar processor performance
    • D. B. Noonburg and J. P. Shen, "Theoretical modeling of superscalar processor performance", in MICRO-27, 1994.
    • (1994) MICRO-27
    • Noonburg, D.B.1    Shen, J.P.2
  • 33
    • 0035177240 scopus 로고    scopus 로고
    • Modeling superscalar processors via statistical simulation
    • S. Nussbaum and J. E. Smith, "Modeling superscalar processors via statistical simulation", in PACT-10, 2001.
    • (2001) PACT-10
    • Nussbaum, S.1    Smith, J.E.2
  • 37
    • 77956201579 scopus 로고    scopus 로고
    • Combined regression and ranking
    • D. Sculley, "Combined regression and ranking", in KDD-16, 2010.
    • (2010) KDD-16
    • Sculley, D.1
  • 40
    • 80052550981 scopus 로고    scopus 로고
    • Moguls: A model to explore the memory hierarchy for bandwidth improvements
    • G. Sun, C. J. Hughes, C. Kim, J. Zhao, C. Xu, Y. Xie, and Y.-K. Chen, "Moguls: A model to explore the memory hierarchy for bandwidth improvements", in ISCA-38, 2011.
    • (2011) ISCA-38
    • Sun, G.1    Hughes, C.J.2    Kim, C.3    Zhao, J.4    Xu, C.5    Xie, Y.6    Chen, Y.-K.7
  • 41
    • 0001884644 scopus 로고
    • Individual comparisons by ranking methods
    • F. Wilcoxon, "Individual comparisons by ranking methods", Biometrics 1(6), 1945.
    • (1945) Biometrics , vol.1 , Issue.6
    • Wilcoxon, F.1
  • 42
    • 0029194459 scopus 로고
    • The SPLASH-2 programs: Characterization and methodological considerations
    • S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: characterization and methodological considerations", in ISCA-22, 1995.
    • (1995) ISCA-22
    • Woo, S.C.1    Ohara, M.2    Torrie, E.3    Singh, J.P.4    Gupta, A.5
  • 43
    • 0038346244 scopus 로고    scopus 로고
    • SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
    • R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, "SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling", in ISCA-30, 2003.
    • (2003) ISCA-30
    • Wunderlich, R.E.1    Wenisch, T.F.2    Falsafi, B.3    Hoe, J.C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.