NAND flash architectures reducing write amplification through multi-write codes

IEEE Symposium on Mass Storage Systems and Technologies

Volumn , Issue , 2014, Pages

  Odeh, Saher ^a   Cassuto, Yuval ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); VIRTUAL STORAGE;

DEVICE PARAMETERS; MAPPING ARCHITECTURE; NAND FLASH; PROPOSED ARCHITECTURES; REAL-WORLD; WRITE AMPLIFICATIONS;

ARCHITECTURE;

EID: 84905460082     PISSN: 21601968     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MSST.2014.6855549     Document Type: Conference Paper

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