MIC-check: A distributed checkpointing framework for the Intel many integrated cores architecture

HPDC 2014 - Proceedings of the 23rd International Symposium on High-Performance Parallel and Distributed Computing

Volumn , Issue , 2014, Pages 121-124

  Rajachandrasekar, Raghunath ^a   Potluri, Sreeram ^a   Venkatesh, Akshay ^a   Hamidouche, Khaled ^a   Wasi Ur Rahman, Md ^a   Panda, Dhabaleswar K ^a  

^a OHIO STATE UNIVERSITY   (United States)

Author keywords

Checkpointing; I O; Many integrated cores; MPI; Xeon Phi

Indexed keywords

COMPUTER ARCHITECTURE; FAULT TOLERANCE; SUPERCOMPUTERS; SYSTEMS ENGINEERING;

CHECK POINTING; DISTRIBUTED CHECKPOINTING; HETEROGENEOUS HARDWARE; INTEGRATED CORE; MANY-CORE ARCHITECTURE; MPI; PERFORMANCE BOTTLENECKS; XEON PHI;

NETWORK ARCHITECTURE;

EID: 84904410795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2600212.2600713     Document Type: Conference Paper

References (7)

1. Improving File IO performance on Intel Xeon Phi. http://software.intel. com/en-us/blogs/2014/01/07/improving-file-io-performance-on-intel-xeon-phi.
2. Intel MIC Architecture. http://www.intel.com/content/www/us/en/ processors/xeon/xeon-phi-detail.html.
3. XEON-PHI Software Developer's Guide. http://www.intel.com/content/dam/ www/public/us/en/documents/product-briefs/xeon-phi-software-developers-guide. pdf.
4. Top500 Supercomputer List. http://www.top500.org/lists/2013/11, November 2013.
5. Ki S. et al. Early Experiences Porting Scientific Applications to the Many Integrated Core (MIC) Platform. In TACC-Intel Tech. Rep, 2012.
6. Su P. et al. MVAPICH-PRISM: A Proxy-based Communication Framework using InfiniBand and SCIF for Intel MIC clusters. In SC'13, 2013.
7. TACC. Stampede Supercomputer. http://www.top500.org/system/177931.