Emulating reconfigurable arrays for image processing using the MasPar architecture

Proceedings of the International Conference on Parallel Processing

Volumn 3, Issue , 1993, Pages 141-148

  Salinas, Jose ^a   Lombardi, Fabrizio ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY PROCESSING; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); PARALLEL PROCESSING SYSTEMS; RECONFIGURABLE ARCHITECTURES;

COMPUTATIONAL POWER; FAULT TOLERANT SCHEMES; IMAGE DATA; PROCESSING ELEMENTS; RECONFIGURABLE ARRAY; TWO-DIMENSIONAL ARRAYS;

IMAGE PROCESSING;

EID: 84904338417     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1993.79     Document Type: Conference Paper

References (9)

1. R. H. T. Bates and M. J. McDonnell, "Image restoration and reconstruction", Clarendon Press, 1986.
2. V. Cantoni et al., "Parallel image processing primitives". Image analysis and processing, V. Cantoni, S. Levialdi, and G. Musso, eds., Plenum Press. 1986.
3. R. A. Evans, J. V. McCanny and K. W. Wood, "Wafer scale integration based on self organization", Wafer Scale Integration, C. R. Jesshipc and W. R. Moore Eds., Adam Hilger 1986.
4. E. Hall, Computer image processing and recognition. Academic Press, 1979.
5. P. F. Leonard and R. N. Mudge, "System design for local neighborhood processing". Proceedings of SPIE, Vol. 534, 1985. pp. 44-50.
6. MasPar Computer Corporation, MasPar MP-] Standard Programming Manual, MasPar Computer Corporation, 1990.
7. M. Sami and R. Stefanelli, "Reeonfigurable architectures for VLSI processor arrays", Proc. IEEE, Vol. 74. No. 5. May 1986.
8. T. Leighton, "A Survey of algorithms for integrating wafer-scale systolic arrays", Wafer Scale Integration, G. Saucier and J. Trilhe, eds., Elsevier Science Publishers, North-Holland, IFIP, 1986, pp. 177-194.
9. J. A. Trotter and W. R. Moore, "Imperfectly connected 2D arrays for Image Processing", FTCS, January 1989, pp. 88-92.