Write-once-memory-code phase change memory

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Li, Jiayin ^a   Mohanram, Kartik ^a  

^a University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); DATA STORAGE EQUIPMENT; MEMORY ARCHITECTURE;

IDLE CYCLES; MAIN MEMORY; MEMORY CONTROLLER; MEMORY ORGANIZATIONS; MEMORY OVERHEADS; NON-VOLATILE MEMORY APPLICATION; WRITE OPERATIONS;

CACHE MEMORY;

EID: 84903848204     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.194     Document Type: Conference Paper

References (38)

1. H. Li and Y. Chen, Nonvolatile Memory Design Magnetic, Resistive, and Phase Changing. CRC Press, 2011.
2. P. Kogge, K. Bergman, S. Borkar, et al., "Exascale computing study Technology challenges in achieving exascale systems," tech. rep., DARPA, 2008.
3. "International Technology Roadmap for Semiconductors," 2011.
4. Y. Xie, "Future memory and interconnect technologies," in Proc. Design Automation and Test in Europe, 2013.
5. S. Kang et al., "A 0.1-um 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-mhz sysnchronous burst-read operation," IEEE Journal of Solid-state Circuits, vol. 42, no. 1, pp. 210-218, 2007.
6. I. Song et al., "A 20nm 1.8V 8GB PRAM with 40MB/s program bandwidth," in Proc. Intl. Solid-state Circuits Conference, 2012.
7. M. K. Qureshi et al., "Improving read performance of phase change memories via write cancellation and write pausing," in Proc. Intl. Symposium on Highperformance Computer Architecture, 2010.
8. W. Wang et al., "Fast phase transitions induced by picosecond electrical pulses on phase change memory cells," Applied Physics Letters, vol. 93, no. 4, pp. 043121- 043121-3, 2008.
9. C. Lee et al., "Performances of GeSnSbTe material for high-speed phase change memory," in Proc. Intl. Symposium on VLSI Technology, Systems and Applications, 2007.
10. S. Lee et al., "Low power and high speed phase-change memory devices with silicon-germanium heating layers," Journal of Vacuum Science and Technology B, vol. 25, no. 4, pp. 1244-1248, 2007.
11. M. K. Qureshi et al., "Preset Improving performance of phase change memories by exploiting asymmetry in write time," in Proc. Intl. Symposium on Computer Architecture, 2012.
12. Y. Kim, S. Yoo, and S. Lee, "Write performance improvement by hiding R drift latency in phase change RAM," in Proc. Design Automation Conference, 2012.
13. S. Kwon et al., "Optimizing video application design for phase-change RAMbased main memory," IEEE Trans. VLSI Systems, vol. 20, no. 11, 2012.
14. L. Jiang et al., "Improving write operations in MLC phase change memory," in Proc. Intl. Symposium on High-performance Computer Architecture, 2012.
15. J. Yue and Y. Zhu, "Making write less blocking for read accesses in phase change memory," in Proc. Intl. Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 2009.
16. S. Cho and H. Lee, "Flip-N-Write A simple deterministic technique to improve PRAM write performance, energy and endurance," in Proc. Intl. Symposium on Microarchitecture, 2009.
17. J. Yue and Y. Zhu, "Accelerating write by exploiting PCM asymmetries," in Proc. Intl. Symposium on High-performance Computer Architecture, 2013.
18. G. Dhiman, R. Ayoub, and T. Rosing, "PDRAM a hybrid PRAM and DRAM main memory system," in Proc. Design Automation Conference, 2009.
19. H. Park, S. Yoo, and S. Lee, "Power management of hybrid DRAM/PRAMbased main memory," in Proc. Design Automation Conference, 2009.
20. J. Dong et al., "Wear rate leveling lifetime enhancement of PRAM with endurance variation," in Proc. Design Automation Conference, 2011.
21. J. Wang et al., "Energy-efficient multi-level cell phase-change memory system with data encoding," in Proc. Intl. Conference on Computer Design, 2011.
22. G. Sun et al., "A frequent-value based pram memory architecture," in Proc. Asia and South Pacific Design Automation Conference, 2011.
23. A. Mirhoseini et al., "Coding-based energy minimization for phase change memory," in Proc. Design Automation Conference, 2012.
24. A. Jiang et al., "Constrained codes for phase-change memories," in Information Theory Workshop, 2010.
25. M. Qin et al., "Time-space cpmstraomed codes for phase-change memories," IEEE Transactions on Information Theory, vol. 59, no. 8, pp. 5102-5114, 2013.
26. W. Xu and T. Zhang, "A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift," IEEE Trans. VLSI Systems, vol. 19, no. 8, pp. 1357-1367, 2011.
27. P. Rosenfeld et al., "DRAMSim2 A cycle accurate memory system simulator," Computer Architecture Letters, vol. 10, no. 1, pp. 16-19, 2011.
28. "SPEC CPU2006," 2006.
29. M. Guthaus et al., "MiBench A free, commercially representative embedded benchmark suite," in Workshop on Workload Characterization, 2001.
30. S. C. Woo et al., "The SPLASH-2 programs Characterization and methodological considerations," in Proc. Intl. Symposium on Computer Architecture, 1995.
31. R. L. Rivest and A. Shamir, "How to reuse a "write-once" memory," Information and Control, vol. 55, pp. 1-19, 1982.
32. A. Jiang et al., "Rank modulation for flash memories," IEEE Trans. Information Theory, vol. 55, no. 6, pp. 2659-2673, 2009.
33. A. Jiang et al., "Correcting charge-constrained errors in the rank-modulation scheme," IEEE Trans. Information Theory, vol. 56, no. 5, pp. 2112-2120, 2010.
34. X. Zhang et al., "WoM-SET Lowering write power of proactive-SET based PCM write strategy using WoM code," in Proc. Intl. Symposium on Low Power Electronics and Design, 2013.
35. Z. Zhang et al., "Design and optimization of large size and low overhead off-chip caches," IEEE Trans. Computers, vol. 53, no. 7, pp. 843-855, 2004.
36. V. Reddi et al., "Pin a binary instrumentation tool for computer architecture research and education," in Workshop on Computer Architecture Education, 2004.
37. B. C. Lee et al., "Architecting phase change memory as a scalable DRAM alternative," in Proc. Intl. Symposium on Computer Architecture, 2009.
38. R. A. Bheda et al., "Energy efficient phase change memory based main memory for future high performance systems," in Proc. Intl. Green Computing Conference and Workshop, 2011.